Estimating the Performance Advantages of Relaxing Consistency in a Shared Memory Multiprocessor. - Josep Torrellas; John L. Hennessy (ICPP (1), 1990)

Share Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates. - Josep Torrellas; Monica S. Lam; John L. Hennessy (ICPP (2), 1990)

Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared Memory Multiprocessor. - Josep Torrellas; John L. Hennessy; Thierry Weil (SIGMETRICS, 1990)

Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System. - Josep Torrellas; Anoop Gupta; John L. Hennessy (ASPLOS, 1992)

Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors: A Summary. - Josep Torrellas; Andrew Tucker; Anoop Gupta (SIGMETRICS, 1993)

Comparing the Performance of the DASH and CEDAR Multiprocessors. - Josep Torrellas; David A. Koufaty; David A. Padua (ICPP (2), 1994)

An efficient algorithm for the run-time parallelization of DOACROSS loops. - Ding-Kai Chen; Josep Torrellas; Pen-Chung Yew (SC, 1994)

False Sharing ans Spatial Locality in Multiprocessor Caches. - Josep Torrellas; Monica S. Lam; John L. Hennessy (IEEE Trans. Computers, 1994)

Optimizing Instruction Cache Performance for Operating System Intensive Workloads. - Josep Torrellas; Chun Xia; Russell L. Daigle (HPCA, 1995)

Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching. - Zheng Zhang 001; Josep Torrellas (ISCA, 1995)

Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors. - Josep Torrellas; Andrew Tucker; Anoop Gupta (J. Parallel Distributed Comput., 1995)

Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors. - Alain Raynaud; Zheng Zhang 001; Josep Torrellas (HPCA, 1996)

Improving the Data Cache Performance of Multiprocessor Operating Systems. - Chun Xia; Josep Torrellas (HPCA, 1996)

The Augmint multiprocessor simulation toolkit for Intel x86 architectures. - Anthony-Trung Nguyen; Maged M. Michael; Arun Sharma; Josep Torrellas (ICCD, 1996)

The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding. - Pedro Trancoso; Josep Torrellas (ICPP, Vol. 3, 1996)

Optimizing Primary Data Caches for Parallel Scientific Applications: The Pool Buffer Approach. - Liuxi Yang; Josep Torrellas (International Conference on Supercomputing, 1996)

Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses. - Chun Xia; Josep Torrellas (ISCA, 1996)

An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors. - Manuel P. Malumbres; José Duato; Josep Torrellas (SPDP, 1996)

Computer architecture education at the University of Illinois: current status and some thoughts. - Josep Torrellas (WCAE@HPCA, 1996)

Data Forwarding in Scalable Shared-Memory Multiprocessors. - David A. Koufaty; Xiangfeng Chen; David K. Poulsen; Josep Torrellas (IEEE Trans. Parallel Distributed Syst., 1996)

The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors. - Pedro Trancoso; Josep Lluís Larriba-Pey; Zheng Zhang 001; Josep Torrellas (HPCA, 1997)

Speeding up the Memory Hierarchy in Flat COMA Multiprocessors. - Liuxi Yang; Josep Torrellas (HPCA, 1997)

Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA. - Zheng Zhang 001; Josep Torrellas (HPCA, 1997)

The Performance of the Cedar Multistage Switching Network. - Josep Torrellas; Zheng Zhang 001 (IEEE Trans. Parallel Distributed Syst., 1997)

An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors. - Venkata Krishnan; Josep Torrellas (IEEE PACT, 1998)

Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma. - Sujoy Basu; Josep Torrellas (HPCA, 1998)

Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors. - Ye Zhang 005; Lawrence Rauchwerger; Josep Torrellas (HPCA, 1998)

Use IRAM for Rasterization. - Yi Kang; Josep Torrellas; Thomas S. Huang (ICIP (3), 1998)

An IRAM architecture for image analysis and pattern recognition. - Yi Kang; Josep Torrellas; Thomas S. Huang (ICPR, 1998)

Comparing Data Forwarding and Prefetching for Communication-induced Misses in Shared-memory MPs. - David A. Koufaty; Josep Torrellas (International Conference on Supercomputing, 1998)

Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-multiprocessor. - Venkata Krishnan; Josep Torrellas (International Conference on Supercomputing, 1998)

A Clustered Approach to Multithreaded Processors. - Venkata Krishnan; Josep Torrellas (IPPS/SPDP, 1998)

Computer architecture education at the University of Illinois. - Josep Torrellas (WCAE@ISCA, 1998)

Optimizing the Instruction Cache Performance of the Operating System. - Josep Torrellas; Chun Xia; Russell L. Daigle (IEEE Trans. Computers, 1998)

Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. - Russell M. Clapp; Ashwini K. Nanda; Josep Torrellas (HPCA, 1999)

Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. - Ye Zhang 005; Lawrence Rauchwerger; Josep Torrellas (HPCA, 1999)

Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. - Qiang Cao; Josep Torrellas; Pedro Trancoso; Josep Lluís Larriba-Pey; Bob Knighten; Youjip Won (ICCD, 1999)

FlexRAM: Toward an Advanced Intelligent Memory System. - Yi Kang; Wei Huang; Seung-Moon Yoo; Diana Keen; Zhenzhou Ge; Vinh Vi Lam; Josep Torrellas; Pratap Pattnaik (ICCD, 1999)

Cache Optimization for Memory-Resident Decision Support Commercial Workloads. - Pedro Trancoso; Josep Torrellas (ICCD, 1999)

Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors. - David A. Koufaty; Josep Torrellas (ICPP, 1999)

Optimization of Instruction Fetch for Decision Support Workloads. - Alex Ramírez; Josep Lluís Larriba-Pey; Carlos Navarro; Xavi Serrano; Mateo Valero; Josep Torrellas (ICPP, 1999)

Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. - José F. Martínez; Josep Torrellas; José Duato (International Conference on Supercomputing, 1999)

Software trace cache. - Alex Ramírez; Josep Lluís Larriba-Pey; Carlos Navarro; Josep Torrellas; Mateo Valero (International Conference on Supercomputing, 1999)

Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability. - Josep Torrellas (PP, 1999)

Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors. - Josep Torrellas; Yan Solihin; Vinh Vi Lam (SC, 1999)

Cache-Only Memory Architectures. - Fredrik Dahlgren; Josep Torrellas (Computer, 1999)

A Chip-Multiprocessor Architecture with Speculative Multithreading. - Venkata Krishnan; Josep Torrellas (IEEE Trans. Computers, 1999)

Comprehensive Hardware and Software Support for Operating Systems to Exploit. - Chun Xia; Josep Torrellas (IEEE Trans. Computers, 1999)

Excel-NUMA: Toward Programmability, Simplicity, and High Performance. - Zheng Zhang 001; Marcelo H. Cintra; Josep Torrellas (IEEE Trans. Computers, 1999)

Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. - Josep Torrellas; Liuxi Yang; Anthony-Trung Nguyen (HPCA, 2000)

Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. - Qiang Cao; Josep Torrellas; H. V. Jagadish (ICCD, 2000)

Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. - Michael C. Huang 001; Jose Renau; Seung-Moon Yoo; Josep Torrellas (Intelligent Memory Systems, 2000)

Adaptively Mapping Code in an Intelligent Memory Architecture. - Yan Solihin; Jaejin Lee; Josep Torrellas (Intelligent Memory Systems, 2000)

Architectural support for scalable speculative parallelization in shared-memory multiprocessors. - Marcelo H. Cintra; José F. Martínez; Josep Torrellas (ISCA, 2000)

SmartApps: An Application Centric Approach to High Performance Computing. - Lawrence Rauchwerger; Nancy M. Amato; Josep Torrellas (LCPC, 2000)

A framework for dynamic energy efficiency and temperature management. - Michael C. Huang 001; Jose Renau; Seung-Moon Yoo; Josep Torrellas (MICRO, 2000)

Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors. - María Jesús Garzarán; Milos Prvulovic; Ye Zhang 005; Josep Torrellas; Alin Jula; Hao Yu 008; Lawrence Rauchwerger (IEEE PACT, 2001)

Automatically Mapping Code on an Intelligent Memory Architecture. - Jaejin Lee; Yan Solihin; Josep Torrellas (HPCA, 2001)

Removing architectural bottlenecks to the scalability of speculative parallelization. - Milos Prvulovic; María Jesús Garzarán; Lawrence Rauchwerger; Josep Torrellas (ISCA, 2001)

L1 data cache decomposition for energy efficiency. - Michael C. Huang 001; Jose Renau; Seung-Moon Yoo; Josep Torrellas (ISLPED, 2001)

The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. - Venkata Krishnan; Josep Torrellas (Int. J. Parallel Program., 2001)

The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. - Michael C. Huang 001; Jose Renau; Seung-Moon Yoo; Josep Torrellas (J. Instr. Level Parallelism, 2001)

Automatic Code Mapping on an Intelligent Memory Architecture. - Yan Solihin; Jaejin Lee; Josep Torrellas (IEEE Trans. Computers, 2001)

Speculative synchronization: applying thread-level speculation to explicitly parallel applications. - José F. Martínez; Josep Torrellas (ASPLOS, 2002)

Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. - Marcelo H. Cintra; Josep Torrellas (HPCA, 2002)

SmartApps: An Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations. - Francis H. Dang; María Jesús Garzarán; Milos Prvulovic; Ye Zhang 005; Alin Jula; Hao Yu 008; Nancy M. Amato; Lawrence Rauchwerger; Josep Torrellas (IPDPS, 2002)

ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. - Milos Prvulovic; Josep Torrellas; Zheng Zhang 001 (ISCA, 2002)

Using a User-Level Memory Thread for Correlation Prefetching. - Yan Solihin; Josep Torrellas; Jaejin Lee (ISCA, 2002)

Energy-efficient hybrid wakeup logic. - Michael C. Huang 001; Jose Renau; Josep Torrellas (ISLPED, 2002)

Cherry: checkpointed early resource recycling in out-of-order microprocessors. - José F. Martínez; Jose Renau; Michael C. Huang 001; Milos Prvulovic; Josep Torrellas (MICRO, 2002)

Software Trace Cache for Commercial Applications. - Alex Ramírez; Josep Lluís Larriba-Pey; Carlos Navarro; Mateo Valero; Josep Torrellas (Int. J. Parallel Program., 2002)

Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. - María Jesús Garzarán; Milos Prvulovic; Víctor Viñals; José María Llabería; Lawrence Rauchwerger; Josep Torrellas (IEEE PACT, 2003)

Design Trade-Offs in High-Throughput Coherence Controllers. - Anthony-Trung Nguyen; Josep Torrellas (IEEE PACT, 2003)

Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. - María Jesús Garzarán; Milos Prvulovic; José María Llabería; Víctor Viñals; Lawrence Rauchwerger; Josep Torrellas (HPCA, 2003)

Positional Adaptation of Processors: Application to Energy Reduction. - Michael C. Huang 001; Jose Renau; Josep Torrellas (ISCA, 2003)

ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. - Milos Prvulovic; Josep Torrellas (ISCA, 2003)

Programming the FlexRAM parallel intelligent memory system. - Basilio B. Fraguela; Jose Renau; Paul Feautrier; David A. Padua; Josep Torrellas (PPoPP, 2003)

Speculative Synchronization: Programmability and Performance for Parallel Codes. - José F. Martínez; Josep Torrellas (IEEE Micro, 2003)

Correlation Prefetching with a User-Level Memory Thread. - Yan Solihin; Jaejin Lee; Josep Torrellas (IEEE Trans. Parallel Distributed Syst., 2003)

iWatcher: Efficient Architectural Support for Software Debugging. - Pin Zhou; Feng Qin 003; Wei Liu 014; Yuanyuan Zhou 001; Josep Torrellas (ISCA, 2004)

AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants. - Pin Zhou; Wei Liu 014; Long Fei; Shan Lu 001; Feng Qin 003; Yuanyuan Zhou 001; Samuel P. Midkiff; Josep Torrellas (MICRO, 2004)

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. - Luis Ceze; Karin Strauss; James Tuck 001; Jose Renau; Josep Torrellas (IEEE Comput. Archit. Lett., 2004)

iWatcher: Simple, General Architectural Support for Software Debugging. - Pin Zhou; Feng Qin 003; Wei Liu 014; Yuanyuan Zhou 001; Josep Torrellas (IEEE Micro, 2004)

Prototyping Architectural Support for Program Rollback Using FPGAs. - Radu Teodorescu; Josep Torrellas (FCCM, 2005)

Thread-Level Speculation on a CMP can be energy efficient. - Jose Renau; Karin Strauss; Luis Ceze; Wei Liu 014; Smruti R. Sarangi; James Tuck 001; Josep Torrellas (ICS, 2005)

Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. - Jose Renau; James Tuck 001; Wei Liu 014; Luis Ceze; Karin Strauss; Josep Torrellas (ICS, 2005)

Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. - María Jesús Garzarán; Milos Prvulovic; José María Llabería; Víctor Viñals; Lawrence Rauchwerger; Josep Torrellas (ACM Trans. Archit. Code Optim., 2005)

Efficient and flexible architectural support for dynamic monitoring. - Yuanyuan Zhou 001; Pin Zhou; Feng Qin 003; Wei Liu 014; Josep Torrellas (ACM Trans. Archit. Code Optim., 2005)

Accurate and efficient filtering for the Intel thread checker race detector. - Paul Sack; Brian E. Bliss; Zhiqiang Ma; Paul Petersen; Josep Torrellas (ASID, 2006)

CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. - Smruti R. Sarangi; Brian Greskamp; Josep Torrellas (DSN, 2006)

ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers. - Jun Nakano; Pablo Montesinos; Kourosh Gharachorloo; Josep Torrellas (HPCA, 2006)

Bulk Disambiguation of Speculative Threads in Multiprocessors. - Luis Ceze; James Tuck 001; Josep Torrellas; Calin Cascaval (ISCA, 2006)

Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. - Karin Strauss; Xiaowei Shen; Josep Torrellas (ISCA, 2006)

PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection. - Shan Lu 001; Pin Zhou; Wei Liu 014; Yuanyuan Zhou 001; Josep Torrellas (MICRO, 2006)

Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware. - Smruti R. Sarangi; Abhishek Tiwari 002; Josep Torrellas (MICRO, 2006)

Scalable Cache Miss Handling for High Memory-Level Parallelism. - James Tuck 001; Luis Ceze; Josep Torrellas (MICRO, 2006)

POSH: a TLS compiler that exploits program structure. - Wei Liu 014; James Tuck 001; Luis Ceze; Wonsun Ahn; Karin Strauss; Jose Renau; Josep Torrellas (PPoPP, 2006)

Energy-Efficient Thread-Level Speculation. - Jose Renau; Karin Strauss; Luis Ceze; Wei Liu 014; Smruti R. Sarangi; James Tuck 001; Josep Torrellas (IEEE Micro, 2006)

SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. - Radu Teodorescu; Jun Nakano; Josep Torrellas (IEEE Micro, 2006)

Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. - Josep Torrellas (IEEE Micro, 2006)

CAVA: Using checkpoint-assisted value prediction to hide L2 misses. - Luis Ceze; Karin Strauss; James Tuck 001; Josep Torrellas; Jose Renau (ACM Trans. Archit. Code Optim., 2006)

Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking. - Brian Greskamp; Josep Torrellas (PACT, 2007)

Using Register Lifetime Predictions to Protect Register Files against Soft Errors. - Pablo Montesinos; Wei Liu 014; Josep Torrellas (DSN, 2007)

Colorama: Architectural Support for Data-Centric Synchronization. - Luis Ceze; Pablo Montesinos; Christoph von Praun; Josep Torrellas (HPCA, 2007)

CAP: Criticality analysis for power-efficient speculative multithreading. - James Tuck 001; Wei Liu 014; Josep Torrellas (ICCD, 2007)

BulkSC: bulk enforcement of sequential consistency. - Luis Ceze; James Tuck 001; Pablo Montesinos; Josep Torrellas (ISCA, 2007)

ReCycle: : pipeline adaptation to tolerate process variation. - Abhishek Tiwari 002; Smruti R. Sarangi; Josep Torrellas (ISCA, 2007)

Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. - Brian Greskamp; Smruti R. Sarangi; Josep Torrellas (ISCAS, 2007)

A Model for Timing Errors in Processors with Parameter Variation. - Smruti R. Sarangi; Brian Greskamp; Josep Torrellas (ISQED, 2007)

Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. - Karin Strauss; Xiaowei Shen; Josep Torrellas (MICRO, 2007)

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. - Radu Teodorescu; Jun Nakano; Abhishek Tiwari 002; Josep Torrellas (MICRO, 2007)

Estimating design time for system circuits. - Cyrus Bazeghi; Francisco J. Mesa-Martinez; Brian Greskamp; Josep Torrellas; Jose Renau (VLSI-SoC, 2007)

Patching Processor Design Errors with Programmable Hardware. - Smruti R. Sarangi; Satish Narayanasamy; Bruce Carneal; Abhishek Tiwari 002; Brad Calder; Josep Torrellas (IEEE Micro, 2007)

Concurrency control with data coloring. - Luis Ceze; Christoph von Praun; Calin Cascaval; Pablo Montesinos; Josep Torrellas (MSPC, 2008)

DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently. - Pablo Montesinos; Luis Ceze; Josep Torrellas (ISCA, 2008)

Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. - Radu Teodorescu; Josep Torrellas (ISCA, 2008)

EVAL: Utilizing processors with variation-induced timing errors. - Smruti R. Sarangi; Brian Greskamp; Abhishek Tiwari 002; Josep Torrellas (MICRO, 2008)

Facelift: Hiding and slowing down aging in multicores. - Abhishek Tiwari 002; Josep Torrellas (MICRO, 2008)

Capo: a software-hardware interface for practical deterministic multiprocessor replay. - Pablo Montesinos; Matthew Hicks; Samuel T. King; Josep Torrellas (ASPLOS, 2009)

Blueshift: Designing processors for timing speculation from the ground up. - Brian Greskamp; Lu Wan; Ulya R. Karpuzcu; Jeffrey J. Cook; Josep Torrellas; Deming Chen; Craig B. Zilles (HPCA, 2009)

How to build a useful thousand-core manycore system? - Josep Torrellas (IPDPS, 2009)

SigRace: signature-based data race detection. - Abdullah Muzahid; Darío Suárez Gracia; Shanxiang Qi; Josep Torrellas (ISCA, 2009)

BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support. - Wonsun Ahn; Shanxiang Qi; M. Nicolaides; Josep Torrellas; Jae-Woo Lee; Xing Fang; Samuel P. Midkiff; David C. Wong 001 (MICRO, 2009)

The BubbleWrap many-core: popping cores for sequential acceleration. - Ulya R. Karpuzcu; Brian Greskamp; Josep Torrellas (MICRO, 2009)

Light64: lightweight hardware support for data race detection during systematic testing of parallel programs. - Adrian Nistor; Darko Marinov; Josep Torrellas (MICRO, 2009)

Two hardware-based approaches for deterministic multiprocessor replay. - Derek Hower; Pablo Montesinos; Luis Ceze; Mark D. Hill; Josep Torrellas (Commun. ACM, 2009)

The Bulk Multicore architecture for improved programmability. - Josep Torrellas; Luis Ceze; James Tuck 001; Calin Cascaval; Pablo Montesinos; Wonsun Ahn; Milos Prvulovic (Commun. ACM, 2009)

Architectures for Extreme-Scale Computing. - Josep Torrellas (Computer, 2009)

SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization. - James Tuck 001; Wonsun Ahn; Josep Torrellas; Luis Ceze (IEEE Micro, 2009)

LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores. - Brian Greskamp; Ulya R. Karpuzcu; Josep Torrellas (HPCA, 2010)

Extreme scale computing: Challenges and opportunities. - Josep Torrellas; Bill Gropp; Vivek Sarkar; Jaime H. Moreno; Kunle Olukotun (HPCA, 2010)

AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection. - Abdullah Muzahid; Norimasa Otsuki; Josep Torrellas (MICRO, 2010)

InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing. - Adrian Nistor; Darko Marinov; Josep Torrellas (MICRO, 2010)

ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment. - Xuehai Qian; Wonsun Ahn; Josep Torrellas (MICRO, 2010)

Rebound: scalable checkpointing for coherent shared memory. - Rishi Agarwal; Pranav Garg 001; Josep Torrellas (ISCA, 2011)

FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes. - Rishi Agarwal; Josep Torrellas (ISCA, 2011)

Cache-Only Memory Architecture (COMA). - Josep Torrellas (Encyclopedia of Parallel Computing, 2011)

Speculation, Thread-Level. - Josep Torrellas (Encyclopedia of Parallel Computing, 2011)

VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages. - Ulya R. Karpuzcu; Krishna B. Kolluru; Nam Sung Kim; Josep Torrellas (DSN, 2012)

BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks. - Yuelu Duan; Xing Zhou; Wonsun Ahn; Josep Torrellas (HPCA, 2012)

Pacman: Tolerating asymmetric data races with unintrusive hardware. - Shanxiang Qi; Norimasa Otsuki; Lois Orosa Nogueira; Abdullah Muzahid; Josep Torrellas (HPCA, 2012)

BulkSMT: Designing SMT processors for atomic-block execution. - Xuehai Qian; Benjamín Sahelices; Josep Torrellas (HPCA, 2012)

FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper. - Josep Torrellas (ICCD, 2012)

Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs. - Ehsan Totoni; Babak Behzad; Swapnil Ghike; Josep Torrellas (ISPASS, 2012)

Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically. - Abdullah Muzahid; Shanxiang Qi; Josep Torrellas (MICRO, 2012)

2012 International Symposium on Computer Architecture Influential Paper Award. - Josep Torrellas (IEEE Micro, 2012)

Extreme scale computer architecture: Energy efficiency from the ground up. - Josep Torrellas (ASAP, 2013)

DeAliaser: alias speculation using atomic region support. - Wonsun Ahn; Yuelu Duan; Josep Torrellas (ASPLOS, 2013)

Cyrus: unintrusive application-level record-replay for replay parallelism. - Nima Honarmand; Nathan Dautenhahn; Josep Torrellas; Samuel T. King; Gilles Pokam; Cristiano Pereira (ASPLOS, 2013)

Volition: scalable and precise sequential consistency violation detection. - Xuehai Qian; Josep Torrellas; Benjamín Sahelices; Depei Qian (ASPLOS, 2013)

Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. - Aditya Agrawal; Prabhat Jain; Amin Ansari; Josep Torrellas (HPCA, 2013)

Illusionist: Transforming lightweight cores into aggressive cores on demand. - Amin Ansari; Shuguang Feng; Shantanu Gupta; Josep Torrellas; Scott A. Mahlke (HPCA, 2013)

Runnemede: An architecture for Ubiquitous High-Performance Computing. - Nicholas P. Carter; Aditya Agrawal; Shekhar Borkar; Romain Cledat; Howard David; Dave Dunning; Joshua B. Fryman; Ivan Ganev; Roger A. Golliver; Rob C. Knauerhase; Richard Lethin; Benoît Meister; et al. (HPCA, 2013)

EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing. - Ulya R. Karpuzcu; Abhishek A. Sinkar; Nam Sung Kim; Josep Torrellas (HPCA, 2013)

WeeFence: toward making fences free in TSO. - Yuelu Duan; Abdullah Muzahid; Josep Torrellas (ISCA, 2013)

QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs. - Gilles Pokam; Klaus Danne; Cristiano Pereira; Rolf Kassa; Tim Kranich; Shiliang Hu; Justin Emile Gottschlich; Nima Honarmand; Nathan Dautenhahn; Samuel T. King; Josep Torrellas (ISCA, 2013)

BulkCommit: scalable and fast commit of atomic blocks in a lazy multiprocessor environment. - Xuehai Qian; Josep Torrellas; Benjamín Sahelices; Depei Qian (MICRO, 2013)

Coping with Parametric Variation at Near-Threshold Voltages. - Ulya R. Karpuzcu; Nam Sung Kim; Josep Torrellas (IEEE Micro, 2013)

RelaxReplay: record and replay for relaxed-consistency multiprocessors. - Nima Honarmand; Josep Torrellas (ASPLOS, 2014)

Extreme-scale computer architecture: Energy efficiency from the ground up‡. - Josep Torrellas (DATE, 2014)

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules. - Aditya Agrawal; Amin Ansari; Josep Torrellas (HPCA, 2014)

Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks. - Amin Ansari; Asit K. Mishra; Jianping Xu; Josep Torrellas (HPCA, 2014)

Dynamically detecting and tolerating IF-Condition Data Races. - Shanxiang Qi; Abdullah Muzahid; Wonsun Ahn; Josep Torrellas (HPCA, 2014)

Replay debugging: Leveraging record and replay for program debugging. - Nima Honarmand; Josep Torrellas (ISCA, 2014)

OmniOrder: Directory-based conflict serialization of transactions. - Xuehai Qian; Benjamín Sahelices; Josep Torrellas (ISCA, 2014)

Improving JavaScript performance by deconstructing the type system. - Wonsun Ahn; Jiho Choi; Thomas Shull; María Jesús Garzarán; Josep Torrellas (PLDI, 2014)

Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy. - Ehsan Totoni; Josep Torrellas; Laxmikant V. Kalé (SC, 2014)

Asymmetric Memory Fences: Optimizing Both Performance and Implementability. - Yuelu Duan; Nima Honarmand; Josep Torrellas (ASPLOS, 2015)

Many-Core Architecture for NTC: Energy Efficiency from the Ground Up. - Josep Torrellas (Near Threshold Computing, 2016)

WearCore: A Core for Wearable Workloads. - Sanyam Mehta; Josep Torrellas (PACT, 2016)

WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication. - Sergi Abadal; Albert Cabellos-Aparicio; Eduard Alarcón; Josep Torrellas (ASPLOS, 2016)

CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization. - Tanmay Gangwani; Adam Morrison 001; Josep Torrellas (ASPLOS, 2016)

Compiler Support for Software Cache Coherence. - Sanket Tavarageri; Wooil Kim; Josep Torrellas; P. Sadayappan (HiPC, 2016)

Toward Extreme-Scale Processor Chips. - Josep Torrellas (HiPC, 2016)

SCsafe: Logging sequential consistency violations continuously and precisely. - Yuelu Duan; David A. Koufaty; Josep Torrellas (HPCA, 2016)

ScalCore: Designing a core for voltage scalability. - Bhargava Gopireddy; Choungki Song; Josep Torrellas; Nam Sung Kim; Aditya Agrawal; Asit K. Mishra (HPCA, 2016)

Architecting and Programming a Hardware-Incoherent Multiprocessor Cache Hierarchy. - Wooil Kim; Sanket Tavarageri; P. Sadayappan; Josep Torrellas (IPDPS, 2016)

Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures. - Raghavendra Pradyumna Pothukuchi; Amin Ansari; Petros G. Voulgaris; Josep Torrellas (ISCA, 2016)

A MAC protocol for Reliable Broadcast Communications in Wireless Network-on-Chip. - Albert Mestres; Sergi Abadal; Josep Torrellas; Eduard Alarcón; Albert Cabellos-Aparicio (NoCArc@MICRO, 2016)

Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. - Dimitrios Skarlatos 002; Renji Thomas; Aditya Agrawal; Shibin Qin; Robert C. N. Pilawa-Podgurski; Ulya R. Karpuzcu; Radu Teodorescu; Nam Sung Kim; Josep Torrellas (MICRO, 2016)

ReplayConfusion: Detecting cache-based covert channel attacks using record and replay. - Mengjia Yan 001; Yasser Shalabi; Josep Torrellas (MICRO, 2016)

21st Century Computer Architecture. - Mark D. Hill; Sarita V. Adve; Luis Ceze; Mary Jane Irwin; David R. Kaeli; Margaret Martonosi; Josep Torrellas; Thomas F. Wenisch; David A. Wood 001; Katherine A. Yelick (CoRR, 2016)

Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency. - Raghavendra Pradyumna Pothukuchi; Amin Ansari; Bhargava Gopireddy; Josep Torrellas (PACT, 2017)

Multilayer Compute Resource Management with Robust Control Theory. - Raghavendra Pradyumna Pothukuchi; Sweta Yamini Pothukuchi; Petros G. Voulgaris; Josep Torrellas (PACT, 2017)

LORE: A loop repository for the evaluation of compilers. - Zhi Chen 001; Zhangxiaowen Gong; Justin Josef Szaday; David C. Wong 001; David A. Padua; Alexandru Nicolau; Alexander V. Veidenbaum; Neftali Watkinson; Zehra Sura; Saeed Maleki; Josep Torrellas; Gerald DeJong (IISWC, 2017)

ShortCut: Architectural Support for Fast Object Access in Scripting Languages. - Jiho Choi; Thomas Shull; María Jesús Garzarán; Josep Torrellas (ISCA, 2017)

Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks. - Mengjia Yan 001; Bhargava Gopireddy; Thomas Shull; Josep Torrellas (ISCA, 2017)

Xylem: enhancing vertical thermal conduction in 3D processor-memory stacks. - Aditya Agrawal; Josep Torrellas; Sachin Idgunji (MICRO, 2017)

Pageforge: a near-memory content-aware page-merging architecture. - Dimitrios Skarlatos 002; Nam Sung Kim; Josep Torrellas (MICRO, 2017)

Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery. - Amirhossein Mirhosseini; Aditya Agrawal; Josep Torrellas (IEEE Comput. Archit. Lett., 2017)

Biased reference counting: minimizing atomic operations in garbage collection. - Jiho Choi; Thomas Shull; Josep Torrellas (PACT, 2018)

Structured Singular Value Control for Modular Resource Management in Multilayer Computers. - Raghavendra Pradyumna Pothukuchi; Sweta Yamini Pothukuchi; Petros G. Voulgaris; Josep Torrellas (CDC, 2018)

Record-Replay Architecture as a General Security Framework. - Yasser Shalabi; Mengjia Yan 001; Nima Honarmand; Ruby B. Lee; Josep Torrellas (HPCA, 2018)

HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs. - Bhargava Gopireddy; Dimitrios Skarlatos 002; Wenjuan Zhu 002; Josep Torrellas (ISCA, 2018)

Yukta: Multilayer Resource Controllers to Maximize Efficiency. - Raghavendra Pradyumna Pothukuchi; Sweta Yamini Pothukuchi; Petros G. Voulgaris; Josep Torrellas (ISCA, 2018)

Millimeter-Wave Propagation within a Computer Chip Package. - Xavier Timoneda; Sergi Abadal; Albert Cabellos-Aparicio; Dionysios Manessis; Jin Zhou 001; Antonio Franques; Josep Torrellas; Eduard Alarcón (ISCAS, 2018)

InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy. - Mengjia Yan 001; Jiho Choi; Dimitrios Skarlatos 002; Adam Morrison 001; Christopher W. Fletcher; Josep Torrellas (MICRO, 2018)

Defining a high-level programming model for emerging NVRAM technologies. - Thomas Shull; Jian Huang 006; Josep Torrellas (ManLang, 2018)

Medium Access Control in Wireless Network-on-Chip: A Context Analysis. - Sergi Abadal; Albert Mestres; Josep Torrellas; Eduard Alarcón; Albert Cabellos-Aparicio (IEEE Commun. Mag., 2018)

An empirical study of the effect of source-level loop transformations on compiler stability. - Zhangxiaowen Gong; Zhi Chen 001; Justin Josef Szaday; David C. Wong 001; Zehra Sura; Neftali Watkinson; Saeed Maleki; David A. Padua; Alexander V. Veidenbaum; Alexandru Nicolau; Josep Torrellas (Proc. ACM Program. Lang., 2018)

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture. - Sergi Abadal; Josep Torrellas; Eduard Alarcón; Albert Cabellos-Aparicio (IEEE Trans. Parallel Distributed Syst., 2018)

Replica: A Wireless Manycore for Communication-Intensive and Approximate Data. - Vimuth Fernando; Antonio Franques; Sergi Abadal; Sasa Misailovic; Josep Torrellas (ASPLOS, 2019)

PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems. - Apostolos Kokolis; Dimitrios Skarlatos 002; Josep Torrellas (HPCA, 2019)

NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory. - Thomas Shull; Jiho Choi; María Jesús Garzarán; Josep Torrellas (HPCA, 2019)

Designing vertical processors in monolithic 3D. - Bhargava Gopireddy; Josep Torrellas (ISCA, 2019)

SecDir: a secure directory to defeat directory side-channel attacks. - Mengjia Yan 001; Jen-Yang Wen; Christopher W. Fletcher; Josep Torrellas (ISCA, 2019)

Opportunistic Beamforming in Wireless Network-on-Chip. - Sergi Abadal; Adrián Marruedo; Antonio Franques; Hamidreza Taghvaee; Albert Cabellos-Aparicio; Jin Zhou 001; Josep Torrellas; Eduard Alarcón (ISCAS, 2019)

Tangram: Integrated Control of Heterogeneous Computers. - Raghavendra Pradyumna Pothukuchi; Joseph L. Greathouse; Karthik Rao; Christopher Erb; Leonardo Piga; Petros G. Voulgaris; Josep Torrellas (MICRO, 2019)

InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum). - Mengjia Yan 001; Jiho Choi; Dimitrios Skarlatos 002; Adam Morrison 001; Christopher W. Fletcher; Josep Torrellas (MICRO, 2019)

Reusable inline caching for JavaScript performance. - Jiho Choi; Thomas Shull; Josep Torrellas (PLDI, 2019)

AutoPersist: an easy-to-use Java NVM framework based on reachability. - Thomas Shull; Jian Huang 006; Josep Torrellas (PLDI, 2019)

Understanding priority-based scheduling of graph algorithms on a shared-memory platform. - Serif Yesil; Azin Heidarshenas; Adam Morrison 001; Josep Torrellas (SC, 2019)

Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World. - Mengjia Yan 001; Read Sprabery; Bhargava Gopireddy; Christopher W. Fletcher; Roy H. Campbell; Josep Torrellas (IEEE Symposium on Security and Privacy, 2019)

QuickCheck: using speculation to reduce the overhead of checks in NVM frameworks. - Thomas Shull; Jian Huang 006; Josep Torrellas (VEE, 2019)

Maya: Falsifying Power Sidechannels with Operating System Support. - Raghavendra Pradyumna Pothukuchi; Sweta Yamini Pothukuchi; Petros G. Voulgaris; Josep Torrellas (CoRR, 2019)

SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (CoRR, 2019)

SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (PACT, 2020)

Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism. - Dimitrios Skarlatos 002; Apostolos Kokolis; Tianyin Xu; Josep Torrellas (ASPLOS, 2020)

Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors. - Azin Heidarshenas; Tanmay Gangwani; Serif Yesil; Adam Morrison 001; Josep Torrellas (ICS, 2020)

V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging. - Azin Heidarshenas; Serif Yesil; Dimitrios Skarlatos 002; Sasa Misailovic; Adam Morrison 001; Josep Torrellas (ICS, 2020)

Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution. - Jiyong Yu; Namrata Mantri; Josep Torrellas; Adam Morrison 001; Christopher W. Fletcher (ISCA, 2020)

SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Sara S. Baghsorkhi; Josep Torrellas (MICRO, 2020)

P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks. - Apostolos Kokolis; Thomas Shull; Jian Huang 006; Josep Torrellas (MICRO, 2020)

Draco: Architectural and Operating System Support for System Call Security. - Dimitrios Skarlatos 002; Qingrong Chen; Jianyan Chen; Tianyin Xu; Josep Torrellas (MICRO, 2020)

Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis. - Zirui Neil Zhao; Houxiang Ji; Mengjia Yan 001; Jiyong Yu; Christopher W. Fletcher; Adam Morrison 001; Darko Marinov; Josep Torrellas (MICRO, 2020)

Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization. - Serif Yesil; Azin Heidarshenas; Adam Morrison 001; Josep Torrellas (SC, 2020)

Millimeter wave wireless network on chip using deep reinforcement learning. - Suraj Jog; Zikun Liu; Antonio Franques; Vimuth Fernando; Haitham Hassanieh; Sergi Abadal; Josep Torrellas (SIGCOMM Posters and Demos, 2020)

Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures. - Mengjia Yan 001; Christopher W. Fletcher; Josep Torrellas (USENIX Security Symposium, 2020)

MicroScope: Enabling Microarchitectural Replay Attacks. - Dimitrios Skarlatos 002; Mengjia Yan 001; Bhargava Gopireddy; Read Sprabery; Josep Torrellas; Christopher W. Fletcher (IEEE Micro, 2020)

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication. - Xavier Timoneda; Sergi Abadal; Antonio Franques; Dionysios Manessis; Jin Zhou 001; Josep Torrellas; Eduard Alarcón; Albert Cabellos-Aparicio (IEEE Trans. Commun., 2020)

Jamais vu: thwarting microarchitectural replay attacks. - Dimitrios Skarlatos 002; Zirui Neil Zhao; Riccardo Paccagnella; Christopher W. Fletcher; Josep Torrellas (ASPLOS, 2021)

Speculative interference attacks: breaking invisible speculation schemes. - Mohammad Behnia; Prateek Sahu; Riccardo Paccagnella; Jiyong Yu; Zirui Neil Zhao; Xiang Zou; Thomas Unterluggauer; Josep Torrellas; Carlos V. Rozas; Adam Morrison 001; Frank McKeen; Fangfei Liu; et al. (ASPLOS, 2021)

Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores. - Antonio Franques; Sergi Abadal; Haitham Hassanieh; Josep Torrellas (DATE, 2021)

WiDir: A Wireless-Enabled Directory Cache Coherence Protocol. - Antonio Franques; Apostolos Kokolis; Sergi Abadal; Vimuth Fernando; Sasa Misailovic; Josep Torrellas (HPCA, 2021)

Maya: Using Formal Control to Obfuscate Power Side Channels. - Raghavendra Pradyumna Pothukuchi; Sweta Yamini Pothukuchi; Petros G. Voulgaris; Alexander G. Schwing; Josep Torrellas (ISCA, 2021)

Execution Dependence Extension (EDE): ISA Support for Eliminating Fences. - Thomas Shull; Ilias Vougioukas; Nikos Nikoleris; Wendy Elsasser; Josep Torrellas (ISCA, 2021)

One Protocol to Rule Them All: Wireless Network-on-Chip using Deep Reinforcement Learning. - Suraj Jog; Zikun Liu; Antonio Franques; Vimuth Fernando; Sergi Abadal; Josep Torrellas; Haitham Hassanieh (NSDI, 2021)

UniHeap: managing persistent objects across managed runtimes for non-volatile memory. - Daixuan Li; Benjamin Reidys; Jinghan Sun; Thomas Shull; Josep Torrellas; Jian Huang 006 (SYSTOR, 2021)

Speculative taint tracking (STT): a comprehensive protection for speculatively accessed data. - Jiyong Yu; Mengjia Yan 001; Artem Khyzha; Adam Morrison 001; Josep Torrellas; Christopher W. Fletcher (Commun. ACM, 2021)

A Method for Hiding the Increased Non-Volatile Cache Read Latency. - Apostolos Kokolis; Namrata Mantri; Shrikanth Ganapathy; Josep Torrellas; John Kalamatianos (CoRR, 2021)

BabelFish: Fusing Address Translations for Containers. - Dimitrios Skarlatos 002; Umur Darbaz; Bhargava Gopireddy; Nam Sung Kim; Josep Torrellas (IEEE Micro, 2021)

Parallel virtualized memory translation with nested elastic cuckoo page tables. - Jovan Stojkovic; Dimitrios Skarlatos 002; Apostolos Kokolis; Tianyin Xu; Josep Torrellas (ASPLOS, 2022)

Pinned loads: taming speculative loads in secure processors. - Zirui Neil Zhao; Houxiang Ji; Adam Morrison 001; Darko Marinov; Josep Torrellas (ASPLOS, 2022)

Cloak: tolerating non-volatile cache read latency. - Apostolos Kokolis; Namrata Mantri; Shrikanth Ganapathy; Josep Torrellas; John Kalamatianos (ICS, 2022)

Dense dynamic blocks: optimizing SpMM for processors with vector and matrix units using machine learning techniques. - Serif Yesil; José E. Moreira; Josep Torrellas (ICS, 2022)

Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. - Zhangxiaowen Gong; Houxiang Ji; Yao Yao; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (ISCA, 2022)

Binoculars: Contention-Based Side-Channel Attacks Exploiting the Page Walker. - Zirui Neil Zhao; Adam Morrison 001; Christopher W. Fletcher; Josep Torrellas (USENIX Security Symposium, 2022)

Distributed Data Persistency. - Apostolos Kokolis; Antonis Psistakis; Benjamin Reidys; Jian Huang 006; Josep Torrellas (IEEE Micro, 2022)

Untangle: A Principled Framework to Design Low-Leakage, High-Performance Dynamic Partitioning Schemes. - Zirui Neil Zhao; Adam Morrison 001; Christopher W. Fletcher; Josep Torrellas (ASPLOS (3), 2023)

Memory-Efficient Hashed Page Tables. - Jovan Stojkovic; Namrata Mantri; Dimitrios Skarlatos 002; Tianyin Xu; Josep Torrellas (HPCA, 2023)

SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution. - Jovan Stojkovic; Tianyin Xu; Hubertus Franke; Josep Torrellas (HPCA, 2023)

SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM. - Gerasimos Gerogiannis; Serif Yesil; Damitha Lenadora; Dingyuan Cao 002; Charith Mendis; Josep Torrellas (ISCA, 2023)

μManycore: A Cloud-Native CPU for Tail at Scale. - Jovan Stojkovic; Chunao Liu; Muhammad Shahbaz 001; Josep Torrellas (ISCA, 2023)

MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency. - Jovan Stojkovic; Tianyin Xu; Hubertus Franke; Josep Torrellas (ISCA, 2023)

Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-Making. - Gerasimos Gerogiannis; Josep Torrellas (MICRO, 2023)

WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning. - Serif Yesil; Azin Heidarshenas; Adam Morrison 001; Josep Torrellas (PPoPP, 2023)

Defensive ML: Defending Architectural Side-channels with Adversarial Obfuscation. - Hyoungwook Nam; Raghavendra Pradyumna Pothukuchi; Bo Li 026; Nam Sung Kim; Josep Torrellas (CoRR, 2023)

Input-sensitive dense-sparse primitive compositions for GNN acceleration. - Damitha Lenadora; Vimarsh Sathia; Gerasimos Gerogiannis; Serif Yesil; Josep Torrellas; Charith Mendis (CoRR, 2023)

FriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense against Side Channel Attacks. - Hyoungwook Nam; Raghavendra Pradyumna Pothukuchi; Bo Li 026; Nam Sung Kim; Josep Torrellas (PACT, 2024)

Two-Face: Combining Collective and One-Sided Communication for Efficient Distributed SpMM. - Charles Block; Gerasimos Gerogiannis; Charith Mendis; Ariful Azad; Josep Torrellas (ASPLOS (2), 2024)

Everywhere All at Once: Co-Location Attacks on Public Cloud FaaS. - Zirui Neil Zhao; Adam Morrison 001; Christopher W. Fletcher; Josep Torrellas (ASPLOS (1), 2024)

Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud. - Zirui Neil Zhao; Adam Morrison 001; Christopher W. Fletcher; Josep Torrellas (ASPLOS (2), 2024)

HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures. - Gerasimos Gerogiannis; Sriram Aananthakrishnan; Josep Torrellas; Ibrahim Hur (HPCA, 2024)

MINOS: Distributed Consistency and Persistency Protocol Implementation & Offloading to SmartNICs. - Antonis Psistakis; Fabien Chaix; Josep Torrellas (HPCA, 2024)

HADES: Hardware-Assisted Distributed Transactions in the Age of Fast Networks and SmartNICs. - Apostolos Kokolis; Antonis Psistakis; Benjamin Reidys; Jian Huang 006; Josep Torrellas (ISCA, 2024)

EcoFaaS: Rethinking the Design of Serverless Environments for Energy Efficiency. - Jovan Stojkovic; Nikoleta Iliakopoulou; Tianyin Xu; Hubertus Franke; Josep Torrellas (ISCA, 2024)

Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless Environments. - Jovan Stojkovic; Esha Choukse; Enrique Saurez; Íñigo Goiri; Josep Torrellas (MICRO, 2024)

Distributed-Memory Parallel Algorithms for Sparse Matrix and Sparse Tall-and-Skinny Matrix Multiplication. - Isuru Ranawaka; Md Taufique Hussain; Charles Block; Gerasimos Gerogiannis; Josep Torrellas; Ariful Azad (SC, 2024)

Towards Greener LLMs: Bringing Energy-Efficiency to the Forefront of LLM Inference. - Jovan Stojkovic; Esha Choukse; Chaojie Zhang; Íñigo Goiri; Josep Torrellas (CoRR, 2024)

Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud (Extended Version). - Zirui Neil Zhao; Adam Morrison 001; Christopher W. Fletcher; Josep Torrellas (CoRR, 2024)

Transforming the Hybrid Cloud for Emerging AI Workloads. - Deming Chen; Alaa Youssef; Ruchi Pendse; André Schleife; Bryan K. Clark; Hendrik F. Hamann; Jingrui He; Teodoro Laino; Lav R. Varshney; Yuxiong Wang; Avirup Sil; Reyhaneh Jabbarvand; et al. (CoRR, 2024)

Chameleon: Adaptive Caching and Scheduling for Many-Adapter LLM Inference Environments. - Nikoleta Iliakopoulou; Jovan Stojkovic; Chloe Alverti; Tianyin Xu; Hubertus Franke; Josep Torrellas (CoRR, 2024)

Practical Online Reinforcement Learning for Microprocessors With Micro-Armed Bandit. - Gerasimos Gerogiannis; Josep Torrellas (IEEE Micro, 2024)

CXLfork: Fast Remote Fork over CXL Fabrics. - Chloe Alverti; Stratos Psomadakis; Burak Ocalan; Shashwat Jaiswal; Tianyin Xu; Josep Torrellas (ASPLOS (2), 2025)

TAPAS: Thermal- and Power-Aware Scheduling for LLM Inference in Cloud Platforms. - Jovan Stojkovic; Chaojie Zhang; Íñigo Goiri; Esha Choukse; Haoran Qiu; Rodrigo Fonseca; Josep Torrellas; Ricardo Bianchini (ASPLOS (2), 2025)

Concord: Rethinking Distributed Coherence for Software Caches in Serverless Environments. - Jovan Stojkovic; Chloe Alverti; Alan Andrade; Nikoleta Iliakopoulou; Hubertus Franke; Tianyin Xu; Josep Torrellas (HPCA, 2025)

DynamoLLM: Designing LLM Inference Clusters for Performance and Energy Efficiency. - Jovan Stojkovic; Chaojie Zhang; Íñigo Goiri; Josep Torrellas; Esha Choukse (HPCA, 2025)

MeshSlice: Efficient 2D Tensor Parallelism for Distributed DNN Training. - Hyoungwook Nam; Gerasimos Gerogiannis; Josep Torrellas (ISCA, 2025)

HardHarvest: Hardware-Supported Core Harvesting for Microservices. - Jovan Stojkovic; Chunao Liu; Muhammad Shahbaz 001; Josep Torrellas (ISCA, 2025)

EMT: An OS Framework for New Memory Translation Architectures. - Siyuan Chai; Jiyuan Zhang 003; Jongyul Kim 001; Alan Wang; Fan Chung; Jovan Stojkovic; Weiwei Jia 001; Dimitrios Skarlatos 002; Josep Torrellas; Tianyin Xu (OSDI, 2025)

DECA: A Near-Core LLM Decompression Accelerator Supporting Out-of-Order Invocation. - Gerasimos Gerogiannis; Stijn Eyerman; Evangelos Georganas; Wim Heirman; Josep Torrellas (CoRR, 2025)

COGNATE: Acceleration of Sparse Tensor Programs on Emerging Hardware using Transfer Learning. - Chamika Sudusinghe; Gerasimos Gerogiannis; Damitha Lenadora; Charles Block; Josep Torrellas; Charith Mendis (CoRR, 2025)