Investment vs. Yield Relationship for Memories and IP in SOC. - Joseph A. Reynick (ITC, 2004)

Innovative Practices on DFT for AI Chips. - Iris Ma; Hui King Lau; Joseph A. Reynick; Yu Huang 005 (VTS, 2019)

Proposed Standardization of Heterogenous Integrated Chiplet Models. - Anthony Mastroianni; Benjamin Kerr; Jawad Nasrullah; Kevin Cameron; Hockshan James Wong; David Ratchkov; Joseph A. Reynick (3DIC, 2021)

Affordable and Comprehensive Testing of 3-D Stacked Die Devices. - Jean-François Côté; Jeff Fan; Sean Shen; Givargis Danialy 001; Marcin Lipinski; Michael Garbers; Wu Yang; Martin Keim; Andreas Glowatz; Joe Reynick; Ayush Patel; Joanna Michna (IEEE Des. Test, 2022)