Joseph F. Ryan

Affiliations:
  • University of Virginia


According to our database1, Joseph F. Ryan authored at least 12 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019

2018
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits, 2016

2015
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Error-energy analysis of hardware logarithmic approximation methods for low power applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011
An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010
Flexible Circuits and Architectures for Ultralow Power.
Proc. IEEE, 2010

System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2008
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Analyzing and modeling process balance for sub-threshold circuit design.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007


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