Analyzing and modeling process balance for sub-threshold circuit design. - Joseph F. Ryan 002; Jiajing Wang; Benton H. Calhoun (ACM Great Lakes Symposium on VLSI, 2007)

Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation. - Joseph F. Ryan 002; Benton H. Calhoun (ISQED, 2008)

A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. - Joseph F. Ryan 002; Benton H. Calhoun (CICC, 2010)

System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms. - Benton H. Calhoun; Sudhanshu Khanna; Yanqing Zhang 002; Joseph F. Ryan 002; Brian P. Otis (ISCAS, 2010)

Flexible Circuits and Architectures for Ultralow Power. - Benton H. Calhoun; Joseph F. Ryan 002; Sudhanshu Khanna; Mateja Putic; John C. Lach (Proc. IEEE, 2010)

An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal. - Joseph F. Ryan 002; Sudhanshu Khanna; Benton H. Calhoun (ISLPED, 2011)

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. - Carlos Tokunaga; Joseph F. Ryan 002; Charles Augustine; Jaydeep P. Kulkarni; Yi-Chun Shih; Stephen T. Kim; Rinkle Jain; Keith A. Bowman; Arijit Raychowdhury; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2014)

Error-energy analysis of hardware logarithmic approximation methods for low power applications. - Alicia Klinefelter; Joseph F. Ryan 002; James W. Tschanz; Benton H. Calhoun (ISCAS, 2015)

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2015)

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2016)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)