A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator. - Joseph Hamilton; Shouli Yan; T. R. Viswanathan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC. - Joseph Hamilton; Shouli Yan; T. R. Viswanathan 001 (CICC, 2012)