A silicon efficient FLEX 6000 programmable logic architecture. - Chiakang Sung; Richard Cliff; Joseph Huang; Bonnie Wang; Khai Nguyen; Xtaobao Wang; Kerry Veenstra; Bruce Pedersen; John Turner (CICC, 1998)

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. - Jeffrey Tyhach; Bonnie Wang; Chiakang Sung; Joseph Huang; Khai Nguyen; Xiaobao Wang; Yan Chong; Philip Pan; Henry Kim; Gopinath Rangan; Tzung-Chin Chang; Johnson Tan (CICC, 2004)

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. - Jeffrey Tyhach; Bonnie Wang; Chiakang Sung; Joseph Huang; Khai Nguyen; Xiaobao Wang; Yan Chong; Philip Pan; Henry Kim; Gopinath Rangan; Tzung-Chin Chang; Johnson Tan (IEEE J. Solid State Circuits, 2005)

Efficient, generalized indoor WiFi GraphSLAM. - Joseph Huang; David Millman; Morgan Quigley; David Stavens; Sebastian Thrun; Alok Aggarwal (ICRA, 2011)

Mining cross-ontology weighted association rules between GO and HPO. - Joseph Huang; Collin Rapp; Young-Rae Cho (BIBM, 2017)

A Deep Learning Analysis of Climate Change, Innovation, and Uncertainty. - Michael Barnett; William Brock; Lars Peter Hansen; Ruimeng Hu; Joseph Huang (CoRR, 2023)