Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. - Nick Brown 002; Maurice Jamieson; Joseph K. L. Lee; Paul Wang (SC Workshops, 2023)

Backporting RISC-V Vector Assembly. - Joseph K. L. Lee; Maurice Jamieson; Nick Brown 002 (ISC Workshops, 2023)

Test-Driving RISC-V Vector Hardware for HPC. - Joseph K. L. Lee; Maurice Jamieson; Nick Brown 002; Ricardo Jesus (ISC Workshops, 2023)

Experiences of running an HPC RISC-V testbed. - Nick Brown 002; Maurice Jamieson; Joseph K. L. Lee (CoRR, 2023)

Quantum Task Offloading with the OpenMP API. - Joseph K. L. Lee; Oliver T. Brown; Mark Bull; Martin Ruefenacht; Johannes Doerfert; Michael Klemm; Martin Schulz 001 (CoRR, 2023)

Sustainable AI: Experiences, Challenges & Recommendations. - Eleanor Broadway; Joseph K. L. Lee; Michèle Weiland (SC Workshops, 2024)

Benchmarking Machine Learning Applications on Heterogeneous Architecture using Reframe. - Christopher Rae; Joseph K. L. Lee; James Richings; Michèle Weiland (CoRR, 2024)

2BP: 2-Stage Backpropagation. - Christopher Rae; Joseph K. L. Lee; James Richings (CoRR, 2024)