Accurate power estimation for large sequential circuits. - Joseph N. Kozhaya; Farid N. Najm (ICCAD, 1997)

Fast power grid simulation. - Sani R. Nassif; Joseph N. Kozhaya (DAC, 2000)

Multi-grid methods for power grid simulation. - Sani R. Nassif; Joseph N. Kozhaya (ISCAS, 2000)

I/O buffer placement methodology for ASICs. - Joseph N. Kozhaya; Sani R. Nassif; Farid N. Najm (ICECS, 2001)

Power estimation for large sequential circuits. - Joseph N. Kozhaya; Farid N. Najm (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Analysis and Design of Power and Ground Networks for VLSI Circuits - Joseph N. Kozhaya (2001)

A multigrid-like technique for power grid analysis. - Joseph N. Kozhaya; Sani R. Nassif; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Power network analysis for ESD robustness in a 90nm ASIC design system. - Ciaran J. Brennan; Joseph N. Kozhaya; Robert A. Proctor (CICC, 2004)

An electrically robust method for placing power gating switches in voltage islands. - Joseph N. Kozhaya; Luay Bakir (CICC, 2004)

A chip-level electrostatic discharge simulation strategy. - Haifeng Qian; Joseph N. Kozhaya; Sani R. Nassif; Sachin S. Sapatnekar (ICCAD, 2004)

Power supply noise aware workload assignment for multi-core systems. - Aida Todri; Malgorzata Marek-Sadowska; Joseph N. Kozhaya (ICCAD, 2008)

Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. - Joseph N. Kozhaya; Phillip J. Restle; Haifeng Qian (ICCAD, 2011)

Subtractive Router for Tree-Driven-Grid Clocks. - Haifeng Qian; Phillip J. Restle; Joseph N. Kozhaya; Clifford L. Gunion (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Pacman: driving nonuniform clock grid loads for low-skew robust clock network. - Nancy Y. Zhou; Phillip J. Restle; Joseph N. Palumbo; Joseph N. Kozhaya; Haifeng Qian; Zhuo Li 001; Charles J. Alpert; Cliff C. N. Sze (SLIP, 2014)