Methodology for I/O cell placement and checking in ASIC designs using area-array power grid. - Patrick H. Buffet; Joseph Natonio; Robert A. Proctor; Yu H. Sun; Gulsun Yasar (CICC, 2000)

A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications. - Ram Kelkar; Dave Flye; Anjali Malladi; Joseph Natonio; Chri Scoville; Ken Short; Pradeep Thiagarajan (SoCC, 2005)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)