A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI. - Babak Mohammadi; Oskar Andersson; Joseph Nguyen; Lorenzo Ciampolini; Andreia Cathelin; Joachim Neves Rodrigues (ESSCIRC, 2016)

Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells. - Lorenzo Ciampolini; Jean-Christophe Lafont; Faress Tissafi Drissi; Jean-Paul Morin; David Turgis; Xavier Jonsson; Cyril Desclèves; Joseph Nguyen (ICCAD, 2016)

RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs. - Joseph Nguyen; David Turgis; David Bonciani; Brice Lhomme; Yann Carminati; Olivier Callen; Guillaume Guirleo; Lorenzo Ciampolini; Gérard Ghibaudo (NATW, 2016)

A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI. - Babak Mohammadi; Oskar Andersson; Joseph Nguyen; Lorenzo Ciampolini; Andreia Cathelin; Joachim Neves Rodrigues (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)