Design Considerations for a Bipolar Implementation of SPARC. - Anant Agrawal; Eric W. Brown 002; Joe Petolino; James R. Peterson (COMPCON, 1988)

Implementing Sparc in ECL. - Emil W. Brown; Anant Agrawal; Trevor Creary; Michael F. Klein; Dave Murata; Joseph Petolino (IEEE Micro, 1990)

microSPARCTM: A Case Study of Scan-Based Debug. - Kalon Holdbrook; Sunil Joshi; Samir Mitra; Joe Petolino; Renu Raman; Michelle Wong (ITC, 1994)

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. - Raymond A. Heald; Ken Shin; Vinita Reddy; I-Feng Kao; Masood Khan; William L. Lynch; Gary Lauterbach; Joe Petolino (IEEE J. Solid State Circuits, 1998)