Joseph A. Reynick

According to our database, Joseph A. Reynick authored at least 4 papers between 2004 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Affordable and Comprehensive Testing of 3-D Stacked Die Devices.

Jean-François Côté, Jeff Fan, Sean Shen, Givargis Danialy, Marcin Lipinski, Michael Garbers, Wu Yang, Martin Keim, Andreas Glowatz, Joe Reynick, Ayush Patel, Joanna Michna

IEEE Des. Test, 2022

2021

Proposed Standardization of Heterogenous Integrated Chiplet Models.

Anthony Mastroianni, Benjamin Kerr, Jawad Nasrullah, Kevin Cameron, Hockshan James Wong, David Ratchkov, Joseph A. Reynick

Proceedings of the IEEE International 3D Systems Integration Conference, 2021

2019

Innovative Practices on DFT for AI Chips.

Iris Ma, Hui King Lau, Joseph A. Reynick, Yu Huang

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2004

Investment vs. Yield Relationship for Memories and IP in SOC.

Joseph A. Reynick

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004