A micropower-compatible time-multiplexed SC speech spectrum analyzer design. - Joseph S. Chang; Yit Chow Tong (IEEE J. Solid State Circuits, 1993)

A parametric formulation of the generalized spectral subtraction method. - Boh Lim Sim; Yit Chow Tong; Joseph Sylvester Chang; Chin-Tuan Tan (IEEE Trans. Speech Audio Process., 1998)

A process-independent threshold voltage inverter-comparator for pulse width modulation applications. - Meng Tong Tan; Joseph S. Chang; Yit Chow Tong (ICECS, 1999)

A novel self-tuning pulse width modulator based on master-slave architecture for a Class D amplifier. - Meng Tong Tan; Joseph Sylvester Chang; Yit Chow Tong (ISCAS (2), 1999)

An investigation on the parameters affecting total harmonic distortion in class D amplifiers. - Meng Tong Tan; Hock-Chuan Chua; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2000)

A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity. - Joseph Sylvester Chang; Bah-Hwee Gwee; Yong Seng Lon; Meng Tong Tan (ISCAS (1), 2001)

A digital Class D amplifier design embodying a novel sampling process and pulse generator. - Huiyun Li; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (4), 2001)

A novel low-voltage low-power wave digital filter bank for an intelligent noise reduction digital hearing instrument. - Meng Tong Tan; Joseph Sylvester Chang; Yit Chow Tong (ISCAS (2), 2001)

Low-voltage micropower asynchronous multiplier for hearing instruments. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (1), 2002)

Low-voltage asynchronous adders for low power and high speed applications. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (1), 2002)

A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems. - Bah-Hwee Gwee; Joseph Sylvester Chang (HIS, 2003)

A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter. - Chien-Chung Chua; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (5), 2003)

A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers. - Bah-Hwee Gwee; Joseph Sylvester Chang; Victor Adrian; H. Amir (ISCAS (4), 2003)

A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File. - Khia-Ho Chang; Bah-Hwee Gwee; Joseph Sylvester Chang (VLSI, 2003)

A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier. - Victor Adrian; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (3), 2004)

A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (2), 2004)

A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers. - Victor Adrian; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (6), 2005)

Low-voltage micropower multipliers with reduced spurious switching. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS (4), 2005)

Design and analysis of a micropower low-voltage bang-bang control class D amplifier. - Tong Ge; Meng Tong Tan; Joseph Sylvester Chang (ISCAS (1), 2005)

Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellation. - Jingbo Yang; Meng Tong Tan; Joseph Sylvester Chang (ISCAS (2), 2005)

A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator. - Bah-Hwee Gwee; Joseph Sylvester Chang; Victor Adrian (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A micropower low-voltage multiplier with reduced spurious switching. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Optimized Algorithm for Computing Invariants of Ordinary Petri Nets. - Chong-Fatt Law; Bah-Hwee Gwee; Joseph S. Chang (ACIS-ICIS, 2006)

Fourier Series Analysis for Nonlinearities Due to the Power Supply Noise in Open-Loop Class D Amplifiers. - Wei Shu; Joseph Sylvester Chang; Tong Ge; Meng Tong Tan (APCCAS, 2006)

An acoustic noise suppression system with reduced musical artifacts. - Victor Adrian; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2006)

Modeling and analysis of PSRR in analog PWM class D amplifiers. - Tong Ge; Joseph Sylvester Chang; Wei Shu (ISCAS, 2006)

Fourier series analysis of the nonlinearities in analog closed-loop PWM class D amplifiers. - Wei Shu; Joseph Sylvester Chang; Tong Ge; Meng Tong Tan (ISCAS, 2006)

A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A Low Energy FFT/IFFT Processor for Hearing Aids. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2007)

Power Supply Noise in Bang-Bang Control Class D Amplifier. - Tong Ge; Joseph Sylvester Chang; Wei Shu (ISCAS, 2007)

Design of several asynchronous-logic macrocells for a low-voltage micropower cell library. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (IET Circuits Devices Syst., 2007)

Low energy 16-bit Booth leapfrog array multiplier using dynamic adders. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (IET Circuits Devices Syst., 2007)

Fast and memory-efficient invariant computation of ordinary Petri nets. - Chong-Fatt Law; Bah-Hwee Gwee; Joseph Sylvester Chang (IET Comput. Digit. Tech., 2007)

Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. - Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (IEEE J. Solid State Circuits, 2007)

PSRR of bridge-tied load PWM Class D Amps. - Tong Ge; Joseph Sylvester Chang; Wei Shu (ISCAS, 2008)

Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis. - Chong-Fatt Law; Bah-Hwee Gwee; Joseph Sylvester Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers. - Tong Ge; Joseph Sylvester Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Bang-Bang Control Class-D Amplifiers: Power-Supply Noise. - Tong Ge; Joseph S. Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

THD of Closed-Loop Analog PWM Class-D Amplifiers. - Wei Shu; Joseph Sylvester Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. - Tong Lin 001; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2009)

A Low THD Analog Class D Amplifier based on Self-oscillating Modulation with Complete Feedback Network. - Wenfeng Yu; Wei Shu; Joseph Sylvester Chang (ISCAS, 2009)

A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids. - Victor Adrian; Joseph S. Chang; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Bang-Bang Control Class D Amplifiers: Total Harmonic Distortion and Supply Noise. - Tong Ge; Joseph S. Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. - Bah-Hwee Gwee; Joseph S. Chang; Yiqiong Shi; Chien-Chung Chua; Kwen-Siong Chong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Power Supply Noise in Analog Audio Class D Amplifiers. - Wei Shu; Joseph Sylvester Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A micropower comparator for high power-efficiency hearing aid class D amplifiers. - Linfei Guo; Tong Ge; Joseph Sylvester Chang (ISCAS, 2010)

Filterless class D amplifiers: power-efficiency and power dissipation. - Tong Ge; Joseph S. Chang (IET Circuits Devices Syst., 2010)

A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters. - Victor Adrian; Joseph S. Chang; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

IMD of Closed-Loop Filterless Class D Amplifiers. - Wei Shu; Joseph Sylvester Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A low-power dual-rail inputs write method for bit-interleaved memory cells. - Junchao Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2011)

Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang; Yin Sun; Kok-Leong Chang (ISCAS, 2011)

Asynchronous DSP for low-power energy-efficient embedded systems. - Yiqiong Shi; Bah-Hwee Gwee; Joseph Sylvester Chang (Microprocess. Microsystems, 2011)

Modeling and Synthesis of Asynchronous Pipelines. - Chong-Fatt Law; Bah-Hwee Gwee; Joseph Sylvester Chang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A comparative study on asynchronous Quasi-Delay-Insensitive templates. - Kok-Leong Chang; Tong Lin 001; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. - Junchao Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. - Weng-Geng Ho; Kwen-Siong Chong; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques. - Kwen-Siong Chong; Joseph S. Chang; Idongesit E. Ebong; Yalcin Yilmaz; Pinaki Mazumder (ISED, 2012)

Challenges of printed electronics on flexible substrates. - Joseph S. Chang; Tong Ge; Edgar Sánchez-Sinencio (MWSCAS, 2012)

Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. - Kwen-Siong Chong; Kok-Leong Chang; Bah-Hwee Gwee; Joseph S. Chang (IEEE J. Solid State Circuits, 2012)

A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS. - Jaeyoung Kim; Kwen-Siong Chong; Joseph Sylvester Chang; Pinaki Mazumder (ACM Great Lakes Symposium on VLSI, 2013)

A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. - Kok-Leong Chang; Tong Lin 001; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2013)

Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2013)

Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. - Kok-Leong Chang; Joseph S. Chang; Bah-Hwee Gwee; Kwen-Siong Chong (IEEE J. Emerg. Sel. Topics Circuits Syst., 2013)

An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. - Tong Lin 001; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (IEEE J. Solid State Circuits, 2013)

Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (APCCAS, 2014)

A Randomized Modulation scheme for filterless digital Class D audio amplifiers. - Victor Adrian; Cui Keer; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2014)

Design of a 5 GS/s fully-digital digital-to-analog converter. - Victor Adrian; Yin Sun; Joseph Sylvester Chang (ISCAS, 2014)

Synthesis of asynchronous QDI circuits using synchronous coding specifications. - Rong Zhou; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang; Weng-Geng Ho (ISCAS, 2014)

A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang; Ne Kyaw Zwa Lwin (ISIC, 2014)

A self-oscillating class D audio amplifier with dual voltage and current feedback. - Salma Nashit; Victor Adrian; Cui Keer; Quoc-An Mai; Bah-Hwee Gwee; Joseph S. Chang (ISIC, 2014)

Design of an output stage for high switching frequency DC-DC converters. - Tian-Shun Ng; Yin Sun; Victor Adrian; Bah-Hwee Gwee; Joseph S. Chang (ISIC, 2014)

Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process. - Joseph S. Chang; Kwen-Siong Chong; Wei Shu; Tong Lin 001; Jize Jiang; Ne Kyaw Zwa Lwin; Yang Kang (MWSCAS, 2014)

Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag. - Tong Ge; Joseph S. Chang; Tong Lin 001; Lei Zhang; Lim Geok Soon (MWSCAS, 2014)

Analysis and design of PWM-in-PWM-out Class D Amplifiers. - Linfei Guo; Tong Ge; Yang Kang; Huiqiao He; Joseph Sylvester Chang (MWSCAS, 2014)

An investigation into the effect of carrier generators on power supply noise in PWM Class D amplifiers. - Huiqiao He; Tong Ge; Linfei Guo; Joseph S. Chang (MWSCAS, 2014)

A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Amplifier. - Linfei Guo; Tong Ge; Joseph Sylvester Chang (IEEE J. Solid State Circuits, 2014)

A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). - Rong Zhou; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A novel low-power high-efficiency 3-state filterless bang-bang class D amplifier. - Huiqiao He; Yang Kang; Jia Yu 004; Linfei Guo; Tong Ge; Joseph S. Chang (ICECS, 2015)

High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). - Weng-Geng Ho; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2015)

A novel subthreshold voltage reference featuring 17ppm/°C TC within -40°C to 125°C and 75dB PSRR. - Jize Jiang; Wei Shu; Joseph Sylvester Chang; Jingyuan Liu (ISCAS, 2015)

Design of a variable-delay window ADC for switched-mode DC-DC converters. - Yin Sun; Victor Adrian; Joseph S. Chang (ISCAS, 2015)

A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. - Rong Zhou; Kwen-Siong Chong; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2015)

Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. - Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (IET Circuits Devices Syst., 2015)

An Ultralow-Power Overcurrent Protection Circuit for Micropower Class D Amplifiers. - Linfei Guo; Tong Ge; Joseph S. Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. - Nan Liu 002; Kwen-Siong Chong; Weng-Geng Ho; Bah-Hwee Gwee; Joseph Sylvester Chang (DATE, 2016)

An investigation of THD of a BTL Class D amplifier. - Tong Ge; Huiqiao He; Jia Zhou 002; Yang Kang; Joseph S. Chang (ISCAS, 2016)

High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. - Weng-Geng Ho; Nan Liu 002; Kyaw Zwa Lwin Ne; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2016)

Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process. - Jize Jiang; Wei Shu; Kwen-Siong Chong; Tong Lin 001; Ne Kyaw Zwa Lwin; Joseph Sylvester Chang; Jingyuan Liu (ISCAS, 2016)

Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. - Tong Lin 001; Kwen-Siong Chong; Wei Shu; Ne Kyaw Zwa Lwin; Jize Jiang; Joseph S. Chang (ISCAS, 2016)

Fully-additive printed electronics: Process Development Kit. - Jia Zhou 002; Tong Ge; Joseph S. Chang (ISCAS, 2016)

A review on supply modulators for Envelope-Tracking Power Amplifiers. - Huiqiao He; Tong Ge; Joseph Sylvester Chang (ISIC, 2016)

A review of audio Class D amplifiers. - Yang Kang; Tong Ge; Huiqiao He; Joseph S. Chang (ISIC, 2016)

A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network. - Qianqian Liu; Victor Adrian; Bah-Hwee Gwee; Joseph S. Chang (ISIC, 2016)

Substrate thickness effect on transformer. - Jia Yu 004; Tong Ge; Huiqiao He; Joseph S. Chang (ISIC, 2016)

Review: A fully-additive printed electronics process with very-low process variations (Bent and unbent substrates) and PDK. - Tong Ge; Jia Zhou 002; Yang Kang; Joseph S. Chang (ISCAS, 2017)

A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation. - Qianqian Liu; Victor Adrian; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2017)

A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters. - Yin Sun; Victor Adrian; Joseph S. Chang (ISCAS, 2017)

A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters. - Cui Keer; Victor Adrian; Yin Sun; Bah-Hwee Gwee; Joseph S. Chang (NEWCAS, 2017)

Guest Editorial Organic/Printed Electronics: A Circuits and Systems Perspective. - Joseph S. Chang; Antonio F. Facchetti; Robert Reuss (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches. - Joseph S. Chang; Antonio F. Facchetti; Robert Reuss (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point. - Jize Jiang; Wei Shu; Joseph S. Chang (IEEE J. Solid State Circuits, 2017)

A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands. - F. N. U. Juanda; Wei Shu; Joseph S. Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Printed Electronics: Effects of Bending and a Self-Compensation Means. - Jia Zhou 002; Tong Ge; Joseph S. Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. - Kwen-Siong Chong; Weng-Geng Ho; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS. - Qing Liu 005; Wei Shu; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Single-Event-Transient Resilient Memory for DSP in Space Applications. - Ne Kyaw Zwa Lwin; H. Sivaramakrishnan; Kwen-Siong Chong; Tong Lin 001; Wei Shu; Joseph S. Chang (DSP, 2018)

Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things. - Wei Shu; Jize Jiang; Kwen-Siong Chong; Joseph Sylvester Chang (DSP, 2018)

A Circuit for Reducing the Reverse Current in DCM DC-DC Converters. - Yin Sun; Victor Adrian; Tong Ge; Joseph S. Chang (DSP, 2018)

An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters. - Yong Qu; Wei Shu; Joseph S. Chang (ISCAS, 2018)

Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters. - Yin Sun; Victor Adrian; Joseph S. Chang (ISCAS, 2018)

Flexible Hybrid Electronics: Review and Challenges. - Tong Ge; Zhou Jia; Joseph S. Chang (ISCAS, 2018)

A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range. - Jize Jiang; Wei Shu; Joseph S. Chang (IEEE J. Solid State Circuits, 2018)

A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters. - Cui Keer; Victor Adrian; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 1-GS/s 11-Bit SAR-Assisted Pipeline ADC With 59-dB SNDR in 65-nm CMOS. - Qing Liu 005; Wei Shu; Joseph S. Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. - Weng-Geng Ho; Kwen-Siong Chong; Kyaw Zwa Lwin Ne; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme. - F. N. U. Juanda; Wei Shu; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. - Kwen-Siong Chong; Aparna Shreedhar; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Chao Wang 096; Jun Zhou 017; Bah-Hwee Gwee; Joseph S. Chang (AsianHOST, 2019)

A Monolithic I2V2-Controlled Dual-Phase LED Matrix Driver for Automotive Adaptive Driving Beam (ADB) Headlighting. - Yong Qu; Wei Shu; Joseph S. Chang (CICC, 2019)

A 30V 2A Real-Time Programmable Solid-State Circuit Breaker with Improved Detection-Speed and Enhanced Power-Efficiency. - Yong Qu; Wei Shu; Yang Kang; Joseph S. Chang (ESSCIRC, 2019)

Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. - Aparna Shreedhar; Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; L. Nalangilli; Wei Shu; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2019)

A Fully Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics With Self-Compensation for Bending: Codesign From Materials, Design, Fabrication, and Applications. - Joseph S. Chang; Tong Ge (Proc. IEEE, 2019)

Flexible Electronic Skin: From Humanoids to Humans. - Ravinder Dahiya; Deji Akinwande; Joseph S. Chang (Proc. IEEE, 2019)

Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller. - Kwen-Siong Chong; Ne Kyaw Zwa Lwin; Wei Shu; Joseph S. Chang (ISCAS, 2020)

A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. - Weng-Geng Ho; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2020)

A Low-Profile High-Efficiency Fast Battery Charger With Unifiable Constant-Current and Constant-Voltage Regulation. - Yong Qu; Wei Shu; Lei Qiu 002; Yen-Cheng Kuan; Shiuh-Hua Wood Chiang; Joseph S. Chang (IEEE Trans. Circuits Syst., 2020)

A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power Inputs. - Yong Qu; Wei Shu; Yen-Cheng Kuan; Shiuh-Hua Wood Chiang; Yue Li; Zixian Zheng; Joseph S. Chang (CICC, 2021)

Normalized Differential Power Analysis - for Ghost Peaks Mitigation. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Weng-Geng Ho; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2021)

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. - Kwen-Siong Chong; Jun-Sheng Ng; Juncheng Chen; Ne Kyaw Zwa Lwin; Nay Aung Kyaw; Weng-Geng Ho; Joseph Sylvester Chang; Bah-Hwee Gwee (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Non-profiling based Correlation Optimization Deep Learning Analysis. - Juncheng Chen; Jun-Sheng Ng; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Zhiping Lin 001; Joseph Sylvester Chang; Bah-Hwee Gwee (ISCAS, 2022)

An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies. - Jinhen Lee; Victor Adrian; Joseph S. Chang; Yin Sun; Sun-Yang Tay (ISCAS, 2022)

An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. - Jun-Sheng Ng; Juncheng Chen; Nay Aung Kyaw; Ne Kyaw Zwa Lwin; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (ISCAS, 2022)

A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors. - Sun-Yang Tay; Victor Adrian; Joseph S. Chang; Jinhen Lee; Bah-Hwee Gwee (ISCAS, 2022)

A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. - Jun-Sheng Ng; Juncheng Chen; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters. - Jinhen Lee; Victor Adrian; Sun-Yang Tay; Yanshan Xie; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2023)

An Accurate Digital Inductor Current Sensor for Current-Ripple-Based DC-DC Converters. - Yanshan Xie; Victor Adrian; Sun-Yang Tay; Jinhen Lee; Pak Kwong Chan; Joseph S. Chang (ISCAS, 2023)

A Novel Voltage-Controlled Oscillator Linearized by a Resistorless Dynamic-Degeneration Technique. - Jinhen Lee; Victor Adrian; Bah-Hwee Gwee; Joseph Sylvester Chang (APCCAS, 2024)

An Energy-Efficient and High-Accuracy Spiking Neural Network Utilizing Asynchronous CORDIC for On-FPGA STDP Learning. - Shirui Sheng; Kwen-Siong Chong; Jun-Sheng Ng; Zhiping Lin 001; Joseph S. Chang; Bah-Hwee Gwee (APCCAS, 2024)

A 134-μW 50-MHz Quasi-Dynamic Comparator with A Novel Clock-Free Regenerative Latch. - Sun-Yang Tay; Victor Adrian; Rouli Fang; Yanshan Xie; Joseph S. Chang (CICC, 2024)

A Novel Multi-Error-Lock-Trace (MELT) Test Structure for SET/SEU Characterization of Radiation-Hardened-By-Design Cells. - Rouli Fang; Kwen-Siong Chong; Kyaw Zwa Lwin Ne; Wei Shu; Sun-Yang Tay; Joseph Sylvester Chang (MWSCAS, 2024)

A Novel Energy-Efficient Continuous-Time Hysteretic VCO-Based Comparator. - Jinhen Lee; Victor Adrian; Kinglouis Steven Tantra; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2025)

Live Demonstration: AI-based System Latchup Detection and Protection for COTS Systems. - Yin Sun; Junkai Zhao; Rouli Fang; Tony Zhang; Kwen-Siong Chong; Wei Shu; Joseph S. Chang (ISCAS, 2025)

A Novel High-Accuracy Inductor-Current Estimator for Digitally-Controlled Synchronous DC-DC Buck Converters. - Yanshan Xie; Victor Adrian; Jinhen Lee; Joseph S. Chang (ISCAS, 2025)

An Adaptive AI-based Approach to Detect and Protect COTS Systems against Micro-Single-Event-Latchups (μ-SELs) and SELs. - Junkai Zhao; Yin Sun; Tony Zhang; Kwen-Siong Chong; Wei Shu; Joseph S. Chang (ISCAS, 2025)

Single-Ended/Differential Wideband Track-and-Hold Amplifier in 22-nm FD-SOI CMOS Process. - Zixian Zheng; Wei Shu; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2025)