TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. - Peter Y.-T. Hsu; Joseph T. Rahmeh; Edward S. Davidson; Jacob A. Abraham (ISCA, 1985)

FAUST: An MOS Fault Simulator with Timing Information. - Hsi-Ching Shih; Joseph T. Rahmeh; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. - Prithviraj Banerjee; Joseph T. Rahmeh; Craig B. Stunkel; V. S. S. Nair; Kaushik Roy 001; Jacob A. Abraham (FTCS, 1988)

CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits. - Daniel G. Saab; Robert B. Mueller-Thuns; David T. Blaauw; Jacob A. Abraham; Joseph T. Rahmeh (ICCAD, 1988)

Measurement-Based Performance Models of Numerical Problems on Loosely-Coupled Systems - Joseph T. Rahmeh (1988)

Automatic Generation of Behavioral Models from Switch-Level Descriptions. - David T. Blaauw; Daniel G. Saab; Robert B. Mueller-Thuns; Jacob A. Abraham; Joseph T. Rahmeh (DAC, 1989)

Parallel-concurrent fault simulation. - Daniel G. Saab; Ibrahim N. Hajj; Joseph T. Rahmeh (ICCD, 1989)

Fault grading of large digital systems. - Daniel G. Saab; Robert B. Mueller-Thuns; David T. Blaauw; Joseph T. Rahmeh; Jacob A. Abraham (ICCD, 1990)

Hierarchical multi-level fault simulation of large systems. - Daniel G. Saab; Robert B. Mueller-Thuns; David T. Blaauw; Joseph T. Rahmeh; Jacob A. Abraham (J. Electron. Test., 1990)

Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. - Prithviraj Banerjee; Joseph T. Rahmeh; Craig B. Stunkel; V. S. S. Nair; Kaushik Roy 001; Vijay Balasubramanian; Jacob A. Abraham (IEEE Trans. Computers, 1990)

Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. - Sankaran Karthik; Indira de Souza; Joseph T. Rahmeh; Jacob A. Abraham (ICCD, 1991)

Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation. - Shien-Tai Pan; Kimming So; Joseph T. Rahmeh (ASPLOS, 1992)

Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. - Dah-Cherng Yuan; Lawrence T. Pillage; Joseph T. Rahmeh (DAC, 1993)

Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits. - Robert B. Mueller-Thuns; Joseph T. Rahmeh; Jacob A. Abraham; Jalal A. Wehbeh; Daniel G. Saab (Simul., 1993)