Optimizing inter-nest data locality. - Mahmut T. Kandemir; Ismail Kadayif; Alok N. Choudhary; Joseph Zambreno (CASES, 2002)

Enhancing Compiler Techniques for Memory Energy Optimizations. - Joseph Zambreno; Mahmut T. Kandemir; Alok N. Choudhary (EMSOFT, 2002)

Flexible Software Protection Using Hardware/Software Codesign Techniques. - Joseph Zambreno; Alok N. Choudhary; Rahul Simha; Bhagirath Narahari (DATE, 2004)

Addressing application integrity attacks using a reconfigurable architecture. - Joseph Zambreno; Rahul Simha; Alok N. Choudhary (FPGA, 2004)

Flow Monitoring in High-Speed Networks with 2D Hash Tables. - David Nguyen; Joseph Zambreno; Gokhan Memik (FPL, 2004)

Design and Evaluation of an FPGA Architecture for Software Protection. - Joseph Zambreno (FPL, 2004)

Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. - Joseph Zambreno; David Nguyen; Alok N. Choudhary (FPL, 2004)

Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures. - Joseph Zambreno; Daniel Honbo; Alok N. Choudhary (FCCM, 2005)

CODESSEAL: Compiler/FPGA Approach to Secure Applications. - Olga Gelbart; Paul Ott; Bhagirath Narahari; Rahul Simha; Alok N. Choudhary; Joseph Zambreno (ISI, 2005)

Performance Study of a Compiler/Hardware Approach to Embedded Systems Security. - Kripashankar Mohan; Bhagirath Narahari; Rahul Simha; Paul Ott; Alok N. Choudhary; Joseph Zambreno (ISI, 2005)

SAFE-OPS: An approach to embedded software security. - Joseph Zambreno; Alok N. Choudhary; Rahul Simha; Bhagirath Narahari; Nasir D. Memon (ACM Trans. Embed. Comput. Syst., 2005)

MineBench: A Benchmark Suite for Data Mining Workloads. - Ramanathan Narayanan; Berkin Özisikyilmaz; Joseph Zambreno; Gokhan Memik; Alok N. Choudhary (IISWC, 2006)

An Architectural Characterization Study of Data Mining and Bioinformatics Workloads. - Berkin Özisikyilmaz; Ramanathan Narayanan; Joseph Zambreno; Gokhan Memik; Alok N. Choudhary (IISWC, 2006)

High-Performance Software Protection Using Reconfigurable Architectures. - Joseph Zambreno; Daniel Honbo; Alok N. Choudhary; Rahul Simha; Bhagirath Narahari (Proc. IEEE, 2006)

Interactive presentation: An FPGA implementation of decision tree classification. - Ramanathan Narayanan; Daniel Honbo; Gokhan Memik; Alok N. Choudhary; Joseph Zambreno (DATE, 2007)

Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction. - Sailesh Pati; Ramanathan Narayanan; Gokhan Memik; Alok N. Choudhary; Joseph Zambreno (FPT, 2007)

Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads. - Ramanathan Narayanan; Berkin Özisikyilmaz; Gokhan Memik; Alok N. Choudhary; Joseph Zambreno (International Conference on Computational Science (3), 2007)

Microarchitectures for Managing Chip Revenues under Process Variations. - Abhishek Das; Serkan Ozdemir; Gokhan Memik; Joseph Zambreno; Alok N. Choudhary (IEEE Comput. Archit. Lett., 2007)

An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. - Abhishek Das; Sanchit Misra; Sumeet Joshi; Joseph Zambreno; Gokhan Memik; Alok N. Choudhary (DATE, 2008)

Design and analysis of efficient reconfigurable wavelet filters. - Amit Pande; Joseph Zambreno (EIT, 2008)

Experiments in attacking FPGA-based embedded systems using differential power analysis. - Song Sun; Zijun Yan; Joseph Zambreno (EIT, 2008)

Polymorphic wavelet architectures using reconfigurable hardware. - Amit Pande; Joseph Zambreno (FPL, 2008)

Mining Association Rules with systolic trees. - Song Sun; Joseph Zambreno (FPL, 2008)

Evaluating the effects of cache redundancy on profit. - Abhishek Das; Berkin Özisikyilmaz; Serkan Ozdemir; Gokhan Memik; Joseph Zambreno; Alok N. Choudhary (MICRO, 2008)

A Reconfigurable Platform for Frequent Pattern Mining. - Song Sun; Michael Steffen; Joseph Zambreno (ReConFig, 2008)

Automated software attack recovery using rollback and huddle. - Jesse Sathre; Joseph Zambreno (Des. Autom. Embed. Syst., 2008)

An FPGA-Based Network Intrusion Detection Architecture. - Abhishek Das; David Nguyen; Joseph Zambreno; Gokhan Memik; Alok N. Choudhary (IEEE Trans. Inf. Forensics Secur., 2008)

Hardware-enforced fine-grained isolation of untrusted code. - Eugen Leontie; Gedare Bloom; Bhagirath Narahari; Rahul Simha; Joseph Zambreno (SecuCode@CCS, 2009)

Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems. - Eugen Leontie; Gedare Bloom; Bhagirath Narahari; Rahul Simha; Joseph Zambreno (CSE (2), 2009)

Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores. - Amit Pande; Joseph Zambreno (CSE (2), 2009)

Architectural Support for Automated Software Attack Detection, Recovery, and Prevention. - Jesse Sathre; Alex Baumgarten; Joseph Zambreno (CSE (2), 2009)

An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform. - Amit Pande; Joseph Zambreno (ISVLSI, 2009)

Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure. - Michael Steffen; Joseph Zambreno (TPCG, 2009)

Providing secure execution environments with a last line of defense against Trojan circuit attacks. - Gedare Bloom; Bhagirath Narahari; Rahul Simha; Joseph Zambreno (Comput. Secur., 2009)

Demonstrable differential power analysis attacks on real-world FPGA-based embedded systems. - Song Sun; Zijun Yan; Joseph Zambreno (Integr. Comput. Aided Eng., 2009)

Detecting/preventing information leakage on the memory bus due to malicious hardware. - Abhishek Das; Gokhan Memik; Joseph Zambreno; Alok N. Choudhary (DATE, 2010)

CANSCID-CUDA. - Michael Steffen; Veerendra Allada; Phillip H. Jones; Joseph Zambreno (MEMOCODE, 2010)

Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels. - Michael Steffen; Joseph Zambreno (MICRO, 2010)

A hardware pipeline for accelerating ray traversal algorithms on streaming processors. - Michael Steffen; Joseph Zambreno (SASP, 2010)

A Reconfigurable Architecture for Secure Multimedia Delivery. - Amit Pande; Joseph Zambreno (VLSI Design, 2010)

Preventing IC Piracy Using Reconfigurable Logic Barriers. - Alex Baumgarten; Akhilesh Tyagi; Joseph Zambreno (IEEE Des. Test Comput., 2010)

Reconfigurable hardware implementation of a modified chaotic filter bank scheme. - Amit Pande; Joseph Zambreno (Int. J. Embed. Syst., 2010)

Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. - Justin Rilling; David Graziano; Jamin Hitchcock; Tim Meyer; Xinying Wang 004; Phillip H. Jones; Joseph Zambreno (ICCD, 2011)

Using Chaotic Maps for Encrypting Image and Video Content. - Amit Pande; Prasant Mohapatra; Joseph Zambreno (ISM, 2011)

Architectures for Simultaneous Coding and Encryption Using Chaotic Maps. - Amit Pande; Joseph Zambreno; Prasant Mohapatra (ISVLSI, 2011)

Teaching graphics processing and architecture using a hardware prototyping approach. - Michael Steffen; Phillip H. Jones; Joseph Zambreno (MSE, 2011)

Efficient mapping and acceleration of AES on custom multi-core architectures. - Amit Pande; Joseph Zambreno (Concurr. Comput. Pract. Exp., 2011)

A case study in hardware Trojan design and implementation. - Alex Baumgarten; Michael Steffen; Matthew Clausman; Joseph Zambreno (Int. J. Inf. Sec., 2011)

Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining. - Song Sun; Joseph Zambreno (IEEE Trans. Parallel Distributed Syst., 2011)

Embedded Multimedia Security Systems - Algorithms and Architectures. - Amit Pande; Joseph Zambreno (Springer, 2012)

Design and evaluation of a delay-based FPGA Physically Unclonable Function. - Aaron Mills; Sudhanshu Vyas; Michael Patterson; Christopher Sabotta; Phillip H. Jones; Joseph Zambreno (ICCD, 2012)

Shepard: A fast exact match short read aligner. - Chad Nelson; Kevin Townsend; Bhavani Satyanarayana Rao; Phillip H. Jones; Joseph Zambreno (MEMOCODE, 2012)

The secure wavelet transform. - Amit Pande; Joseph Zambreno (J. Real Time Image Process., 2012)

Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform. - Madhu Monga; Manoj Karkee; Song Sun; Lakshmi Kiran Tondehal; Brian L. Steward; Atul G. Kelkar; Joseph Zambreno (ICCS, 2012)

Improving System Predictability and Performance via Hardware Accelerated Data Structures. - Chetan Kumar Ng; Sudhanshu Vyas; Jonathan A. Shidal; Ron K. Cytron; Christopher D. Gill; Joseph Zambreno; Phillip H. Jones (ICCS, 2012)

An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. - Song Sun; Madhu Monga; Phillip H. Jones; Joseph Zambreno (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression. - Amit Pande; Joseph Zambreno (ACM Trans. Embed. Comput. Syst., 2012)

Reduce, Reuse, Recycle (R3): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms. - Kevin Townsend; Joseph Zambreno (ASAP, 2013)

Polarity Trend Analysis of Public Sentiment on YouTube. - Amar Krishna; Joseph Zambreno; Sandeep Krishnan (COMAD, 2013)

Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. - Chetan Kumar Ng; Sudhanshu Vyas; Ron K. Cytron; Christopher D. Gill; Joseph Zambreno; Phillip H. Jones (ICCS, 2013)

Increasing GPU throughput using kernel interleaved thread block scheduling. - Mihir Awatramani; Joseph Zambreno; Diane T. Rover (ICCD, 2013)

A multi-faceted approach to FPGA-based Trojan circuit detection. - Michael Patterson; Aaron Mills; Ryan A. Scheel; Julie Tillman; Evan Dye; Joseph Zambreno (VTS, 2013)

Securing Multimedia Content Using Joint Compression and Encryption. - Amit Pande; Prasant Mohapatra; Joseph Zambreno (IEEE Multim., 2013)

Hardware architectural support for control systems and sensor processing. - Sudhanshu Vyas; Adwait Gupte; Christopher D. Gill; Ron K. Cytron; Joseph Zambreno; Phillip H. Jones (ACM Trans. Embed. Comput. Syst., 2013)

A chaotic encryption scheme for real-time embedded systems: design and implementation. - Amit Pande; Joseph Zambreno (Telecommun. Syst., 2013)

Towards scalable monitoring and maintenance of rechargeable batteries. - Aaron Mills; Joseph Zambreno (EIT, 2014)

An Efficient Architecture for Floating-Point Eigenvalue Decomposition. - Xinying Wang 004; Joseph Zambreno (FCCM, 2014)

Cache design for mixed criticality real-time systems. - N. G. Chetan Kumar; Sudhanshu Vyas; Ron K. Cytron; Christopher D. Gill; Joseph Zambreno; Phillip H. Jones (ICCD, 2014)

Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications. - Mihir Awatramani; Joseph Zambreno; Diane T. Rover (ICPP Workshops, 2014)

CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search. - Osama G. Attia; Tyler Johnson; Kevin Townsend; Phillip H. Jones; Joseph Zambreno (IPDPS Workshops, 2014)

An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition. - Xinying Wang 004; Joseph Zambreno (IPDPS Workshops, 2014)

A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach. - Xinying Wang 004; Phillip H. Jones; Joseph Zambreno (ISVLSI, 2014)

A high performance systolic architecture for k-NN classification. - Kevin Townsend; Phillip H. Jones; Joseph Zambreno (MEMOCODE, 2014)

An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis. - Sudhanshu Vyas; Chetan Kumar Ng; Joseph Zambreno; Christopher D. Gill; Ron Cytron; Phillip H. Jones (IEEE Embed. Syst. Lett., 2014)

Hardware-software architecture for priority queue management in real-time and embedded systems. - N. G. Chetan Kumar; Sudhanshu Vyas; Ron K. Cytron; Christopher D. Gill; Joseph Zambreno; Phillip H. Jones (Int. J. Embed. Syst., 2014)

Hardware Architecture for Video Authentication Using Sensor Pattern Noise. - Amit Pande; Shaxun Chen; Prasant Mohapatra; Joseph Zambreno (IEEE Trans. Circuits Syst. Video Technol., 2014)

Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications. - Mihir Awatramani; Xian Zhu; Joseph Zambreno; Diane T. Rover (PACT, 2015)

k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator. - Kevin R. Townsend; Song Sun; Tyler Johnson; Osama G. Attia; Phillip H. Jones; Joseph Zambreno (EIT, 2015)

A multi-phase approach to floating-point compression. - Kevin R. Townsend; Joseph Zambreno (EIT, 2015)

A software configurable coprocessor-based state-space controller. - Aaron Mills; Pei Zhang 009; Sudhanshu Vyas; Joseph Zambreno; Phillip H. Jones (FPL, 2015)

A project-based embedded systems design course using a reconfigurable SoC platform. - Daniel Roggow; Paul Uhing; Phillip H. Jones; Joseph Zambreno (MSE, 2015)

Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. - Osama G. Attia; Alex Grieve; Kevin R. Townsend; Phillip H. Jones; Joseph Zambreno (ReConFig, 2015)

A software configurable and parallelized coprocessor architecture for LQR control. - Pei Zhang 009; Aaron Mills; Joseph Zambreno; Phillip H. Jones (ReConFig, 2015)

A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. - Kevin R. Townsend; Osama G. Attia; Phillip H. Jones; Joseph Zambreno (Int. J. Reconfigurable Comput., 2015)

An FPGA Architecture for the Recovery of WPA/WPA2 Keys. - Tyler Johnson; Daniel Roggow; Phillip H. Jones; Joseph Zambreno (J. Circuits Syst. Comput., 2015)

Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform. - Madhu Monga; Daniel Roggow; Manoj Karkee; Song Sun; Lakshmi Kiran Tondehal; Brian L. Steward; Atul G. Kelkar; Joseph Zambreno (Microprocess. Microsystems, 2015)

A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. - Xinying Wang 004; Phillip H. Jones; Joseph Zambreno (SIGARCH Comput. Archit. News, 2015)

Evidence-based planning to broaden the participation of women in electrical and computer engineering. - Diane T. Rover; Joseph Zambreno; Mani Mina; Phillip H. Jones; Lora Leigh Chrystal (FIE, 2016)

Parallelizing Latent Semantic Indexing using an FPGA-based architecture. - Xinying Wang 004; Joseph Zambreno (ICCD, 2016)

ONAC: Optimal number of active cores detector for energy efficient GPU computing. - Xian Zhu; Mihir Awatramani; Diane T. Rover; Joseph Zambreno (ICCD, 2016)

Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling. - Aaron Mills; Phillip H. Jones; Joseph Zambreno (IPDPS Workshops, 2016)

RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing. - Chad Nelson; Kevin R. Townsend; Osama G. Attia; Phillip H. Jones; Joseph Zambreno (IEEE Trans. Parallel Distributed Syst., 2016)

A Reconfigurable Architecture for the Detection of Strongly Connected Components. - Osama G. Attia; Kevin R. Townsend; Phillip H. Jones; Joseph Zambreno (ACM Trans. Reconfigurable Technol. Syst., 2016)

An embedded scalable linear model predictive hardware-based controller using ADMM. - Pei Zhang 009; Joseph Zambreno; Phillip H. Jones (ASAP, 2017)

A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization. - Murad Qasaimeh; Joseph Zambreno; Phillip H. Jones (IPDPS Workshops, 2017)

The design and integration of a software configurable and parallelized coprocessor architecture for LQR control. - Pei Zhang 009; Aaron Mills; Joseph Zambreno; Phillip H. Jones (J. Parallel Distributed Comput., 2017)

A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. - Murad Qasaimeh; Joseph Zambreno; Phillip H. Jones (FPL, 2018)

Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection. - Xian Zhu; Robert Wernsman; Joseph Zambreno (ICPP, 2018)

An FPGA-based Hardware Accelerator for Iris Segmentation. - Joe Avey; Phillip H. Jones; Joseph Zambreno (ReConFig, 2018)

HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. - Matthew Cauwels; Joseph Zambreno; Phillip H. Jones (ReConFig, 2018)

Work-in-Progress: Real-Time Modeling for Intrusion Detection in Automotive Controller Area Network. - Habeeb Olufowobi; Gedare Bloom; Clinton Young; Joseph Zambreno (RTSS, 2018)

ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits. - Alex Grieve; Michael Davies; Phillip H. Jones; Joseph Zambreno (IEEE Trans. Computers, 2018)

An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators. - Saunak Saha; Henry Duwe; Joseph Zambreno (ASAP, 2019)

Anomaly Detection Approach Using Adaptive Cumulative Sum Algorithm for Controller Area Network. - Habeeb Olufowobi; Uchenna Ezeobi; Eric Muhati; Gaylon Robinson; Clinton Young; Joseph Zambreno; Gedare Bloom (AutoSec@CODASPY, 2019)

Automotive Intrusion Detection Based on Constant CAN Message Frequencies Across Vehicle Driving Modes. - Clinton Young; Habeeb Olufowobi; Gedare Bloom; Joseph Zambreno (AutoSec@CODASPY, 2019)

Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. - Murad Qasaimeh; Joseph Zambreno; Phillip H. Jones; Kristof Denolf; Jack Lo; Kees A. Vissers (FCCM, 2019)

Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. - Murad Qasaimeh; Kristof Denolf; Jack Lo; Kees A. Vissers; Joseph Zambreno; Phillip H. Jones (ICESS, 2019)

Survey of Automotive Controller Area Network Intrusion Detection Systems. - Clinton Young; Joseph Zambreno; Habeeb Olufowobi; Gedare Bloom (IEEE Des. Test, 2019)

ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation. - Mohammad Pivezhandi; Phillip H. Jones; Joseph Zambreno (ASAP, 2020)

Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2. - Brian Kempa; Pei Zhang 009; Phillip H. Jones; Joseph Zambreno; Kristin Yvonne Rozier (FORMATS, 2020)

Towards Reverse Engineering Controller Area Network Messages Using Machine Learning. - Clinton Young; Jordan Svoboda; Joseph Zambreno (WF-IoT, 2020)

Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict. - Joshua R. Bertram; Peng Wei; Joseph Zambreno (CoRR, 2020)

SAIDuCANT: Specification-Based Automotive Intrusion Detection Using Controller Area Network (CAN) Timing. - Habeeb Olufowobi; Clinton Young; Joseph Zambreno; Gedare Bloom (IEEE Trans. Veh. Technol., 2020)

CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks. - Saunak Saha; Henry Duwe; Joseph Zambreno (J. Signal Process. Syst., 2020)

An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. - Murad Qasaimeh; Joseph Zambreno; Phillip H. Jones (ASAP, 2021)

Benchmarking vision kernels and neural network inference accelerators on embedded platforms. - Murad Qasaimeh; Kristof Denolf; Alireza Khodamoradi; Michaela Blott; Jack Lo; Lisa Halder; Kees A. Vissers; Joseph Zambreno; Phillip H. Jones (J. Syst. Archit., 2021)

Reverse Engineering Controller Area Network Messages Using Unsupervised Machine Learning. - Uchenna Ezeobi; Habeeb Olufowobi; Clinton Young; Joseph Zambreno; Gedare Bloom (IEEE Consumer Electron. Mag., 2022)

A Fast Markov Decision Process-Based Algorithm for Collision Avoidance in Urban Air Mobility. - Joshua R. Bertram; Peng Wei; Joseph Zambreno (IEEE Trans. Intell. Transp. Syst., 2022)

An FPGA Implementation of SipHash. - Benjamin Welte; Joseph Zambreno (IPDPS Workshops, 2023)

Efficient Unmanned Aerial Systems Navigation With Collision Avoidance in Dense Urban Environments. - Joshua R. Bertram; Joseph Zambreno; Peng Wei (IEEE Trans. Intell. Transp. Syst., 2023)