LURU: global-scope FPGA technology mapping with content-addressable memories. - Joshua M. Lucas; Raymond R. Hoare; Ivan S. Kourtev; Alex K. Jones (ICECS, 2004)

Optimizing Technology Mapping for FPGAs Using CAMs. - Joshua M. Lucas; Raymond Hoare; Alex K. Jones (FCCM, 2005)

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. - Gayatri Mehta; Justin Stander; Joshua M. Lucas; Raymond R. Hoare; Brady Hunsaker; Alex K. Jones (J. Low Power Electron., 2006)

Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). - Joshua M. Lucas; Raymond Hoare; Ivan S. Kourtev; Alex K. Jones (Microprocess. Microsystems, 2006)

Linking Compilation and Visualization for Massively Parallel Programs. - Alex K. Jones; Raymond R. Hoare; Joseph St. Onge; Joshua M. Lucas; Shuyi Shao; Rami G. Melhem (IPDPS, 2007)