An a-FPGA architecture for relative timing based asynchronous designs. - Jotham Vaddaboina Manoranjan; Kenneth S. Stevens (ReConFig, 2014)

Qualifying Relative Timing Constraints for Asynchronous Circuits. - Jotham Vaddaboina Manoranjan; Kenneth S. Stevens (ASYNC, 2016)

Reconfigurable circuit for implementation of family of 4-phase latch protocols. - Jotham Vaddaboina Manoranjan; Kenneth S. Stevens (FPL, 2016)

Design of a multi-style and multi-frequency FPGA. - Jotham Vaddaboina Manoranjan; Solomon Surya Tej Mano Sajjan; Vivek B. Gujari; Kenneth S. Stevens (VLSI-SoC, 2016)