3D DfT architecture for pre-bond and post-bond testing. - Erik Jan Marinissen; Chun-Chuan Chi; Jouke Verbree; Mario Konijnenburg (3DIC, 2010)

Test-architecture optimization for TSV-based 3D stacked ICs. - Brandon Noia; Sandeep Kumar Goel; Krishnendu Chakrabarty; Erik Jan Marinissen; Jouke Verbree (ETS, 2010)

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. - Jouke Verbree; Erik Jan Marinissen; Philippe Roussel; Dimitrios Velenis (ETS, 2010)

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. - Mottaqiallah Taouil; Said Hamdioui; Jouke Verbree; Erik Jan Marinissen (ITC, 2010)

A structured and scalable test access architecture for TSV-based 3D stacked ICs. - Erik Jan Marinissen; Jouke Verbree; Mario Konijnenburg (VTS, 2010)

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. - Brandon Noia; Krishnendu Chakrabarty; Sandeep Kumar Goel; Erik Jan Marinissen; Jouke Verbree (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper. - Erik Jan Marinissen; Chun-Chuan Chi; Mario Konijnenburg; Jouke Verbree (J. Electron. Test., 2012)