A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. - Joung-Wook Moon; Sung-Geun Kim; Dae Hyun Kwon; Woo-Young Choi (CICC, 2014)

A 0.4-V, 90 ∼ 350-MHz PLL With an Active Loop-Filter Charge Pump. - Joung-Wook Moon; Kwang-Chun Choi; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM. - Joung-Wook Moon; Hye-Sung Yoo; Hundai Choi; Il-Won Park; Seok-Yong Kang; Jun-Bae Kim; Haeyoung Chung; Kiho Kim; Dong-Hun Lee; Ki-Jae Song; Seok-Hun Hyun; Indal Song; et al. (A-SSCC, 2018)

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. - Jin-Seok Heo; Kihan Kim; Dong-Hoon Lee; Chang-Kyo Lee; Daesik Moon; Kiho Kim; Jin-Hyeok Baek; Sung-Woo Yoon; Hui-Kap Yang; Kyungryun Kim; Youngjae Kim; Bokgue Park; et al. (VLSI Circuits, 2019)