Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework. - Joycee Mekie; Supratik Chakraborty; Dinesh K. Sharma (VLSI Design, 2004)

Interface Design for Rationally Clocked GALS Systems. - Joycee Mekie; Supratik Chakraborty; Dinesh K. Sharma; Girish Venkataramani; P. S. Thiagarajan (ASYNC, 2006)

Reasoning about synchronization in GALS systems. - Supratik Chakraborty; Joycee Mekie; Dinesh K. Sharma (Formal Methods Syst. Des., 2006)

Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked Systems. - Joycee Mekie (ASYNC, 2014)

Tutorial T7B: Network on Chips - The Journey Overview. - Joycee Mekie; Sneha N. Ved (VLSID, 2014)

Fault tolerant tactile sensor arrays for prosthesis. - Subrahmanya Teja; Joycee Mekie; John-John Cabibihan; Nitish V. Thakor; Sunil L. Kukreja (BioRob, 2016)

Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique. - Sai Aparna Aketi; Joycee Mekie; Hemal Shah (VLSID, 2018)

Impact of Variations on Synchronizer Performance: An Experimental Study. - Joycee Mekie; Prashansa Mukim; Kimaya Kale (VLSID, 2018)

Should We Code Differently When Using Approximate Circuits? - Ankita Nandi; Chandan Kumar Jha 001; Joycee Mekie (APCCAS, 2019)

SEDA - Single Exact Dual Approximate Adders for Approximate Processors. - Chandan Kumar Jha 001; Joycee Mekie (DAC, 2019)

Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs. - Chandan Kumar Jha 001; Joycee Mekie (DSD, 2019)

Quality Tunable Approximate Adder for Low Energy Image Processing Applications. - Chandan Kumar Jha 001; Ankita Nandi; Joycee Mekie (ICECS, 2019)

Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications. - Pramod Kumar Bharti; Neelam Surana; Joycee Mekie (VLSID, 2019)

Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop. - Shubhanshu Gupta; Joycee Mekie (VLSID, 2019)

Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder. - Pramod Kumar Bharti; Neelam Surana; Joycee Mekie (IET Comput. Digit. Tech., 2019)

PANE: Pluggable Asynchronous Network-on-Chip Simulator. - Sneha N. Ved; Sarabjeet Singh; Joycee Mekie (ACM J. Emerg. Technol. Comput. Syst., 2019)

Energy Efficient Single-Ended 6-T SRAM for Multimedia Applications. - Neelam Surana; Joycee Mekie (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing. - Neelam Surana; Mili Lavania; Abhishek Barma; Joycee Mekie (DATE, 2020)

ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator. - Tom Glint; Jitesh Sah; Manu Awasthi; Joycee Mekie (ICCD, 2020)

FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers. - Chandan Kumar Jha 001; Kailash Prasad; Vibhor Kumar Srivastava; Joycee Mekie (ISCAS, 2020)

SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors. - Chandan Kumar Jha 001; Kailash Prasad; Arun Singh Tomar; Joycee Mekie (ISCAS, 2020)

A Low-Voltage Split Memory Architecture for Binary Neural Networks. - Joydeep Kumar Devnath; Neelam Surana; Joycee Mekie (ISCAS, 2020)

Tunable Inexact Subtracters for Division in Image Processing Applications. - Ankita Nandi; Chandan Kumar Jha 001; Joycee Mekie (MWSCAS, 2020)

A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks. - Joydeep Kumar Devnath; Neelam Surana; Joycee Mekie (VLSID, 2020)

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol. - Sai Aparna Aketi; Smriti Gupta; Huimei Cheng; Joycee Mekie; Peter A. Beerel (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Energy and Error Analysis Framework for Approximate Computing in Mobile Applications. - Chandan Kumar Jha 001; Sneha N. Ved; Ishant Anand; Joycee Mekie (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs. - Kailash Prasad; Aditya Biswas; Joycee Mekie (ICECS, 2021)

FPCAM: Floating Point Configurable Approximate Multiplier for Error Resilient Applications. - Chandan Kumar Jha 001; Sumit Walia; Gagan Kanojia; Joycee Mekie (ISCAS, 2021)

HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy. - Sarabjeet Singh; Neelam Surana; Pranjali Jain; Joycee Mekie; Manu Awasthi (CoRR, 2021)

Learning by Cheating : An End-to-End Zero Shot Framework for Autonomous Drone Navigation. - Praveen Venkatesh; Viraj Shah; Vrutik Shah; Yash Kamble; Joycee Mekie (CoRR, 2021)

Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications. - Chandan Kumar Jha 001; Shreyas Singh; Riddhi Thakker; Manu Awasthi; Joycee Mekie (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications. - Varun Gohil; Sumit Walia; Joycee Mekie; Manu Awasthi (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Analysis of Worst-Case Data Dependent Temporal Approximation in Floating Point Units. - Chandan Kumar Jha 001; Ishita Doshi; Joycee Mekie (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

RHSCC-16T: Radiation Hardened Sextuple Cross Coupled Robust SRAM Design for Radiation Prone Environments. - Pramod Kumar Bharti; Joycee Mekie (ICCD, 2022)

Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads. - Pramod Kumar Bharti; Saurabh Jain; Kamlesh R. Pillai; Sagar Varma Sayyaparaju; Gurpreet S. Kalsi; Joycee Mekie; Sreenivas Subramoney (ISCAS, 2022)

An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs. - Alok Parmar; Kailash Prasad; Nanditha P. Rao; Joycee Mekie (ISCAS, 2022)

FastMem: A Fast Architecture-aware Memory Layout Design. - Alok Parmar; Kailash Prasad; Nanditha P. Rao; Joycee Mekie (ISQED, 2022)

RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments. - Pramod Kumar Bharti; Joycee Mekie (VDAT, 2022)

Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications. - Kailash Prasad; Jinay Dagli; Neel Shah; Mallikarjun Pidagannavar; Joycee Mekie (VDAT, 2022)

Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks. - Neelam Surana; Pramod Kumar Bharti; Bachu Varun Tej; Joycee Mekie (VLSID, 2022)

A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms. - Tom Glint; Chandan Kumar Jha 001; Manu Awasthi; Joycee Mekie (CoRR, 2022)

A 10T, 0.22fJ/Bit/Search Mixed-VT Pseudo Precharge-Free Content Addressable Memory. - Diptesh Datta; Neelam Surana; Anoop Kumar; Joycee Mekie (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation. - Sumit Walia; Bachu Varun Tej; Arpita Kabra; Joydeep Kumar Devnath; Joycee Mekie (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Power-Efficient Approximate Multipliers Leveraging Hybrid CMOS-Memristor Paradigm. - Monika Pokharia; Ravi S. Hegde; Joycee Mekie (APCCAS, 2023)

Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers. - Tom Glint; Kailash Prasad; Jinay Dagli; Krishil Gandhi; Aryan Gupta; Vrajesh Patel; Neel Shah; Joycee Mekie (ASP-DAC, 2023)

PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs. - Sai Shubham; Shubham Pandit; Kailash Prasad; Joycee Mekie (DAC, 2023)

REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet. - Tom Glint; Manu Awasthi; Joycee Mekie (DATE, 2023)

Analysis of Quantization Across DNN Accelerator Architecture Paradigms. - Tom Glint; Chandan Kumar Jha 001; Manu Awasthi; Joycee Mekie (DATE, 2023)

PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM. - Kailash Prasad; Aditya Biswas; Arpita Kabra; Joycee Mekie (DATE, 2023)

Process Variation Resilient Current-Domain Analog In Memory Computing. - Kailash Prasad; Sai Shubham; Aditya Biswas; Joycee Mekie (DATE, 2023)

Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA. - Tom Glint; Aryan Gupta; Daniel Giftson; Gaurav Shah; Vrajesh Patel; Ruchit Chudasama; Sukanya More; Joycee Mekie (ISPASS, 2023)

Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators. - Tom Glint; Chandan Kumar Jha 001; Manu Awasthi; Joycee Mekie (ISPASS, 2023)

Fast and Robust Sense Amplifier for Digital In Memory Computing. - Kailash Prasad; Ayush Srivastava; Nistha Baruah; Joycee Mekie (VLSID, 2023)

Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders. - Chandan Kumar Jha 001; Ankita Nandi; Joycee Mekie (IEEE Trans. Very Large Scale Integr. Syst., 2023)

HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy. - Sarabjeet Singh; Neelam Surana; Kailash Prasad; Pranjali Jain; Joycee Mekie; Manu Awasthi (ACM Trans. Archit. Code Optim., 2023)

CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs. - Tom Glint; Manu Awasthi; Joycee Mekie (ASPDAC, 2024)

Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data. - Tom Glint; Manu Awasthi; Joycee Mekie (ASPDAC, 2024)

DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators. - Tom Glint; Mithil Pechimuthu; Joycee Mekie (DATE, 2024)

FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing. - Yathin Kumar Attuluri; Ruchit Chudasama; Kailash Prasad; Joycee Mekie (VLSID, 2024)

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC. - Saketh Gajawada; Aryan Gupta; Kailash Prasad; Joycee Mekie (VLSID, 2024)

COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators. - Vrajesh Patel; Neel Shah; Aravind Krishna; Tom Glint; Abdul Ronak; Joycee Mekie (VLSID, 2024)

Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications. - Monika Pokharia; Kailash Prasad; Ravi S. Hegde; Joycee Mekie (VLSID, 2024)

SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space. - Kailash Prasad; Neel Shah; Jinay Dagli; Joycee Mekie (VLSID, 2024)

VeriBench: Benchmarking Large Language Models for Verilog Code Generation and Design Synthesis. - Mihir Agarwal; Zaqi Momin; Kailash Prasad; Joycee Mekie (ISCAS, 2025)

DTQ-16T: Double Node Upset Tolerant Quadruple SRAM for Space Applications. - Pramod Kumar Bharti; Govind Prasad; Mukku Pavan Kumar; Joycee Mekie (ISCAS, 2025)

HyCMAx: Power-Efficient Hybrid CMOS-Memristor Based Approximate Dividers for Error-Resilient Applications. - Monika Pokharia; Het Trivedi; Siddharth Doshi; Ravi S. Hegde; Joycee Mekie (VLSID, 2025)

OwlsEye: Real-Time Low-Light Video Instance Segmentation on Edge and Exploration of Fixed-Posit Quantization. - Gaurav Shah; Abhinav Goud; Zaqi Momin; Joycee Mekie (VLSID, 2025)