A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. - Dariusz Kania; Józef Kulisz; Adam Milik (DSD, 2005)

Decomposition of Multi-Output Functions for CPLDs. - Dariusz Kania; Adam Milik; Józef Kulisz (DSD, 2005)

Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. - Dariusz Kania; Józef Kulisz (J. Syst. Softw., 2007)

State machine description oriented towards effective usage of vendor-independent synthesis tools. - Robert Czerwinski; Józef Kulisz (PDeS, 2009)

A PC-based object simulator for supporting PLC software development. - Józef Kulisz; Robert Czerwinski; Jan Mocha; Miroslaw Chmiel (PDeS, 2010)

Generating Time Intervals in Programmable Logic Controllers. - Józef Kulisz; Miroslaw Chmiel; Andrzej Malcher (PDeS, 2013)

An IP-Core Generator for Circuits Performing Arithmetic Multiplication. - Józef Kulisz; Jerzy Mikucki (PDeS, 2013)

An IEC 61131-3-based PLC implemented by means of an FPGA. - Miroslaw Chmiel; Józef Kulisz; Robert Czerwinski; A. Krzyzyk; Marcin Rosol; Patryk Smolarek (Microprocess. Microsystems, 2016)

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs. - Marcin Kubica 002; Dariusz Kania; Józef Kulisz (IEEE Access, 2019)