Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization. - Katherine Shu-Min Li; Jr-Yang Huang (ATS, 2008)

Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint. - Katherine Shu-Min Li; Yu-Chen Hung; Jr-Yang Huang (Asian Test Symposium, 2009)

IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency. - Katherine Shu-Min Li; Yi-Yu Liao; Yuo-Wen Liu; Jr-Yang Huang (Asian Test Symposium, 2009)

Synthesizing Multiple Scan Trees to Optimize Test Application Time. - Katherine Shu-Min Li; Jr-Yang Huang (IEEE Des. Test Comput., 2011)