A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. - Po-Chun Liu; Ju-Hung Hsiao; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2011)

A low cost DPA-resistant 8-bit AES core based on ring oscillators. - Hsing-Ping Fu; Ju-Hung Hsiao; Po-Chun Liu; Hsie-Chia Chang; Chen-Yi Lee (VLSI-DAT, 2012)

A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. - Shu-Yu Hsu; Yingchieh Ho; Yuhwai Tseng; Ting-You Lin; Po-Yao Chang; Jen-Wei Lee; Ju-Hung Hsiao; Siou-Ming Chuang; Tze-Zheng Yang; Po-Chun Liu; Ten-Fang Yang; Ray-Jade Chen; et al. (VLSIC, 2012)

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor. - Jen-Wei Lee; Ju-Hung Hsiao; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2012)