A 1.05-V/0.5-V 15.6-Gb/s NRZ Transmitter Achieving 0.76-pJ/bit Energy Efficiency for Low-Power Memory Interfaces. - Ju-Hyeong Yun; Yong-Gyu Yu; Jongchan Lee; Joo-Hyung Chae (ICEIC, 2025)

SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 Receiver. - Chae-Hyeon Lim; Ju-Hyeong Yun; Yong-Gyu Yu; Joo-Hyung Chae (SMACD, 2025)

SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4. - Yong-Gyu Yu; Ju-Hyeong Yun; Chae-Hyeon Lim; Joo-Hyung Chae (SMACD, 2025)