Low power scheduling method using multiple supply voltages. - Kun-Lin Tsai; Ju-Yueh Lee; Shanq-Jang Ruan; Feipei Lai (ISCAS, 2006)

Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. - Ju-Yueh Lee; Yu Hu 002; Rupak Majumdar; Lei He 001 (ISQED, 2009)

Fault-tolerant resynthesis with dual-output LUTs. - Ju-Yueh Lee; Yu Hu 002; Rupak Majumdar; Lei He 001; Minming Li (ASP-DAC, 2010)

RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. - Samuel B. Luckenbill; Ju-Yueh Lee; Yu Hu 002; Rupak Majumdar; Lei He 001 (DATE, 2010)

In-place decomposition for robustness in FPGA. - Ju-Yueh Lee; Zhe Feng 002; Lei He 001 (ICCAD, 2010)

Fault modeling and characteristics of SRAM-based FPGAs (abstract only). - Naifeng Jing; Ju-Yueh Lee; Chun Zhang; Jiarong Tong; Zhigang Mao; Lei He 001 (FPGA, 2011)

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. - Naifeng Jing; Ju-Yueh Lee; Zhe Feng 002; Weifeng He; Zhigang Mao; Shi-Jie Wen; Rick Wong; Lei He 001 (FPL, 2011)

Mitigating FPGA interconnect soft errors by in-place LUT inversion. - Naifeng Jing; Ju-Yueh Lee; Weifeng He; Zhigang Mao; Lei He 001 (ICCAD, 2011)

In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults. - Wenyao Xu; Jia Wang; Yu Hu 002; Ju-Yueh Lee; Fang Gong; Lei He 001; Majid Sarrafzadeh (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs. - Ju-Yueh Lee; Cheng-Ru Chang; Naifeng Jing; Juexiao Su; Shi-Jie Wen; Rick Wong; Lei He 001 (FPT, 2012)

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. - Naifeng Jing; Ju-Yueh Lee; Zhe Feng 002; Weifeng He; Zhigang Mao; Lei He 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

In-place LUT polarity inVersion to mitigate soft errors for FPGAs. - Juexiao Su; Ju-Yueh Lee; Chang Wu; Lei He (DFT, 2016)