Fully pipelined TSPC barrel shifter for high-speed applications. - R. Pereira; Juan A. Michell; José M. Solana (IEEE J. Solid State Circuits, 1995)

Memory efficient programmable processor chip for inverse Haar transform. - Gustavo A. Ruiz; Juan A. Michell (IEEE Trans. Signal Process., 1998)

VLSI configurable delay commutator for a pipeline split radix FFT architecture. - Jesús García; Juan A. Michell; Angel M. Burón (IEEE Trans. Signal Process., 1999)

Parallel-pipelined architecture for 2-D ICT VLSI implementation. - Juan A. Michell; Gustavo A. Ruiz; Angel M. Burón (ICIP (3), 2003)

High throughput 2D DCT/IDCT processor for video coding. - Gustavo A. Ruiz; Juan A. Michell; Angel M. Burón (ICIP (3), 2005)

Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding. - Gustavo A. Ruiz; Juan A. Michell; Angel M. Burón (IEEE Trans. Signal Process., 2005)

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip. - Gustavo A. Ruiz; Juan A. Michell; Angel M. Burón (J. VLSI Signal Process., 2006)

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC. - Juan A. Michell; José M. Solana; Gustavo A. Ruiz (Signal Process. Image Commun., 2011)

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC. - Gustavo A. Ruiz; Juan A. Michell (Signal Process. Image Commun., 2011)

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV. - Gustavo A. Ruiz; Juan A. Michell (J. Signal Process. Syst., 2011)

A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC. - Miguel A. Manzano; Juan A. Michell; Gustavo A. Ruiz (J. Signal Process. Syst., 2013)

Optimized Hardware Implementation for Forward Quantization of H.264/AVC. - Gustavo A. Ruiz; Juan A. Michell (J. Signal Process. Syst., 2013)