A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. - Juan Antonio Maestro; Daniel Mozos; Hortensia Mecha (DATE, 1998)

A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces. - Juan Antonio Maestro; Daniel Mozos; Julio Septién (EUROMICRO, 1998)

The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. - Juan Antonio Maestro; Daniel Mozos; Román Hermida (DATE, 1999)

New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study. - Juan Antonio Maestro; Daniel Mozos; Raquel Dormido; Pedro Reviriego (Des. Autom. Embed. Syst., 2004)

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. - Oscar Ruano; Pilar Reyes; Juan Antonio Maestro; Luca Sterpone; Pedro Reviriego (DDECS, 2007)

Study of the effects of MBUs on the reliability of a 150 nm SRAM device. - Juan Antonio Maestro; Pedro Reviriego (DAC, 2008)

Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study. - Pilar Reyes; Pedro Reviriego; Juan Antonio Maestro; Oscar Ruano (J. Signal Process. Syst., 2008)

Soft error detection and correction for FFT based convolution using different block lengths. - Pedro Reviriego; Juan Antonio Maestro; Anne O'Donnell; Chris J. Bleakley (IOLTS, 2009)

Performance evaluation of energy efficient ethernet. - Pedro Reviriego; José Alberto Hernández 001; David Larrabeiti; Juan Antonio Maestro (IEEE Commun. Lett., 2009)

Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study. - Juan Antonio Maestro; Pedro Reviriego; Pilar Reyes; Oscar Ruano (Integr., 2009)

A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets. - Juan Antonio Maestro; Pedro Reviriego (Microelectron. Reliab., 2009)

Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS. - Pedro Reviriego; Juan Antonio Maestro (ACM Trans. Design Autom. Electr. Syst., 2009)

Reliability of Single-Error Correction Protected Memories. - Juan Antonio Maestro; Pedro Reviriego (IEEE Trans. Reliab., 2009)

IEEE 802.3az: the road to energy efficient ethernet. - Ken Christensen 001; Pedro Reviriego; Bruce Nordman; Michael Bennett; Mehrgan Mostowfi; Juan Antonio Maestro (IEEE Commun. Mag., 2010)

Burst Transmission for Energy-Efficient Ethernet. - Pedro Reviriego; José Alberto Hernández 001; David Larrabeiti; Juan Antonio Maestro (IEEE Internet Comput., 2010)

Efficient Soft Error-Tolerant Adaptive Equalizers. - Pedro Reviriego; Juan Antonio Maestro; Shih-Fu Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Energy Efficiency in Industrial Ethernet: The Case of Powerlink. - Juan Antonio Maestro; Pedro Reviriego (IEEE Trans. Ind. Electron., 2010)

Reliability analysis of memories protected with BICS and a per-word parity bit. - Pedro Reviriego; Juan Antonio Maestro; Chris J. Bleakley (ACM Trans. Design Autom. Electr. Syst., 2010)

Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors. - Pedro Reviriego; Juan Antonio Maestro; Sanghyeon Baeg (DAC, 2011)

Validation and optimization of TMR protections for circuits in radiation environments. - Oscar Ruano; Juan Antonio Maestro; Pedro Reviriego (DDECS, 2011)

Using Coordinated Transmission with Energy Efficient Ethernet. - Pedro Reviriego; Ken Christensen 001; Alfonso Sánchez-Macián; Juan Antonio Maestro (Networking (1), 2011)

On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance. - Pedro Reviriego; Alfonso Sánchez-Macián; Juan Antonio Maestro (Networking Workshops, 2011)

Fault Tolerant Single Error Correction Encoders. - Juan Antonio Maestro; Pedro Reviriego; Costas Argyrides; Dhiraj K. Pradhan (J. Electron. Test., 2011)

An Initial Evaluation of Energy Efficient Ethernet. - Pedro Reviriego; Ken Christensen 001; Juan Rabanillo; Juan Antonio Maestro (IEEE Commun. Lett., 2011)

Implications of energy efficient Ethernet for hubs and switches. - Pedro Reviriego; Juan Antonio Maestro; Chris J. Bleakley (Int. J. Commun. Networks Distributed Syst., 2011)

On the expected longest length probe sequence for hashing with separate chaining. - Pedro Reviriego; Lars Holst; Juan Antonio Maestro (J. Discrete Algorithms, 2011)

Low-complexity Concurrent Error Detection for convolution with Fast Fourier Transforms. - Chris J. Bleakley; Pedro Reviriego; Juan Antonio Maestro (Microelectron. Reliab., 2011)

Mitigation of permanent faults in adaptive equalizers. - Pedro Reviriego; Shanshan Liu 001; Juan Antonio Maestro (Microelectron. Reliab., 2011)

A fast and efficient technique to apply Selective TMR through optimization. - Oscar Ruano; Juan Antonio Maestro; Pedro Reviriego (Microelectron. Reliab., 2011)

Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability. - David Larrabeiti; Pedro Reviriego; José Alberto Hernández 001; Juan Antonio Maestro; Manuel Urueña (Opt. Switch. Netw., 2011)

Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution. - Pedro Reviriego; Chris J. Bleakley; Juan Antonio Maestro; Anne O'Donnell (IEEE Trans. Computers, 2011)

Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters. - Pedro Reviriego; Chris J. Bleakley; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Mitigating the effects of large multiple cell upsets (MCUs) in memories. - Juan Antonio Maestro; Pedro Reviriego; Sanghyeon Baeg; Shi-Jie Wen; Richard Wong (ACM Trans. Design Autom. Electr. Syst., 2011)

An energy consumption model for Energy Efficient Ethernet switches. - Pedro Reviriego; Vijay Sivaraman; Zhi Zhao; Juan Antonio Maestro; Arun Vishwanath; Alfonso Sánchez-Macián; Craig Russell (HPCS, 2012)

Low Power embedded DRAM caches using BCH code partitioning. - Pedro Reviriego; Alfonso Sánchez-Macián; Juan Antonio Maestro (IOLTS, 2012)

Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate. - Pedro Reviriego; Juan Antonio Maestro; José Alberto Hernández 001; David Larrabeiti (Trans. Emerg. Telecommun. Technol., 2012)

Efficient error detection in Double Error Correction BCH codes for memory applications. - Pedro Reviriego; Costas Argyrides; Juan Antonio Maestro (Microelectron. Reliab., 2012)

Multiple Cell Upset Correction in Memories Using Difference Set Codes. - Pedro Reviriego; Mark F. Flanagan; Shih-Fu Liu; Juan Antonio Maestro (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters. - Pedro Reviriego; Oscar Ruano; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network. - José Luis García-Dorado; Eduardo Magaña; Pedro Reviriego; Mikel Izal; Daniel Morató; Juan Antonio Maestro; Javier Aracil 001; Jorge E. López de Vergara (J. Supercomput., 2012)

Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications. - Shih-Fu Liu; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes. - Pedro Reviriego; Shih-Fu Liu; Juan Antonio Maestro; S. Lee; Nur A. Touba; Rudrajit Datta (DFTS, 2013)

Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values. - Burak Karsli; Pedro Reviriego; M. Fatih Balli; Oguz Ergin; Juan Antonio Maestro (IEEE Comput. Archit. Lett., 2013)

Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction. - Pedro Reviriego; Chris J. Bleakley; Juan Antonio Maestro (IEEE Des. Test, 2013)

Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication. - Juan Antonio Maestro; Pedro Reviriego; Sanghyeon Baeg; Shi-Jie Wen; Richard Wong (Microprocess. Microsystems, 2013)

Low Complexity Concurrent Error Detection for Complex Multiplication. - Salvatore Pontarelli; Pedro Reviriego; Chris J. Bleakley; Juan Antonio Maestro (IEEE Trans. Computers, 2013)

A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only. - Pedro Reviriego; Salvatore Pontarelli; Juan Antonio Maestro; Marco Ottavi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design. - Zhen Gao 001; Pedro Reviriego; Wen Pan; Zhan Xu; Ming Zhao 001; Jing Wang 001; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories. - Pedro Reviriego; Salvatore Pontarelli; Juan Antonio Maestro; Marco Ottavi (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

An Efficient Technique to Protect Serial Shift Registers Against Soft Errors. - Pedro Reviriego; Oscar Ruano; Mark F. Flanagan; Salvatore Pontarelli; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors. - Costas Argyrides; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Reliab., 2013)

Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes. - Pedro Reviriego; Juan Antonio Maestro; Mark F. Flanagan (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation. - Pedro Reviriego; Salvatore Pontarelli; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An experimental power profile of Energy Efficient Ethernet switches. - Vijay Sivaraman; Pedro Reviriego; Zhi Zhao; Alfonso Sánchez-Macián; Arun Vishwanath; Juan Antonio Maestro; Craig Russell (Comput. Commun., 2014)

Efficient Flow Sampling With Back-Annotated Cuckoo Hashing. - Salvatore Pontarelli; Pedro Reviriego; Juan Antonio Maestro (IEEE Commun. Lett., 2014)

Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing. - Pedro Reviriego; Salvatore Pontarelli; Juan Antonio Maestro (IEEE Commun. Lett., 2014)

Exploiting processor features to implement error detection in reduced precision matrix multiplications. - Pedro Reviriego; Serdar Zafer Can; Çagri Eryilmaz; Juan Antonio Maestro; Oguz Ergin (Microprocess. Microsystems, 2014)

Optimized parallel decoding of difference set codes for high speed memories. - Mustafa Demirci; Pedro Reviriego; Juan Antonio Maestro (Microelectron. Reliab., 2014)

A fault tolerant implementation of the Goertzel algorithm. - Zhen Gao 005; Pedro Reviriego; X. Li; Juan Antonio Maestro; Ming Zhao 001; J. Wang (Microelectron. Reliab., 2014)

Efficient implementation of error correction codes in hash tables. - Pedro Reviriego; Salvatore Pontarelli; Juan Antonio Maestro; Marco Ottavi (Microelectron. Reliab., 2014)

A Method to Extend Orthogonal Latin Square Codes. - Pedro Reviriego; Salvatore Pontarelli; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A method to protect Bloom filters from soft errors. - Pedro Reviriego; Salvatore Pontarelli; Juan Antonio Maestro; Marco Ottavi (DFTS, 2015)

Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes. - Salvatore Pontarelli; Pedro Reviriego; Marco Ottavi; Juan Antonio Maestro (IEEE Trans. Computers, 2015)

Efficient Coding Schemes for Fault-Tolerant Parallel Filters. - Zhen Gao 001; Pedro Reviriego; Zhan Xu; Xin Su 001; Jing Wang 001; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Fault Tolerant Parallel Filters Based on Error Correction Codes. - Zhen Gao 001; Pedro Reviriego; Wen Pan; Zhan Xu; Ming Zhao 001; Jing Wang 001; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes. - Pedro Reviriego; Salvatore Pontarelli; Adrian Evans; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Synergetic Use of Bloom Filters for Error Detection and Correction. - Pedro Reviriego; Salvatore Pontarelli; Juan Antonio Maestro; Marco Ottavi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction. - Luis J. Saiz-Adalid; Pedro Reviriego; Pedro J. Gil; Salvatore Pontarelli; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Efficient fault tolerant parallel matrix-vector multiplications. - Zhen Gao 001; Pedro Reviriego; Juan Antonio Maestro (IOLTS, 2016)

Improving counting Bloom filter performance with fingerprints. - Salvatore Pontarelli; Pedro Reviriego; Juan Antonio Maestro (Inf. Process. Lett., 2016)

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs. - Mustafa Demirci; Pedro Reviriego; Juan Antonio Maestro (Microelectron. Reliab., 2016)

DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs. - Pedro Reviriego; Mustafa Demirci; Jesús Tabero; Alberto Regadío; Juan Antonio Maestro (Microelectron. Reliab., 2016)

Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes. - Mustafa Demirci; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Computers, 2016)

Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput. - Salvatore Pontarelli; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Computers, 2016)

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits. - Pedro Reviriego; Mustafa Demirci; Adrian Evans; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes. - Alfonso Sánchez-Macián; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Comment on "Fast Bloom Filters and Their Generalization". - Pedro Reviriego; Kenneth J. Christensen; Juan Antonio Maestro (IEEE Trans. Parallel Distributed Syst., 2016)

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks. - Zhen Gao 001; Pedro Reviriego; Zhan Xu; Xin Su 001; Ming Zhao 001; Jing Wang 001; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code. - Pedro Reviriego; Shanshan Liu 001; Liyi Xiao; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Optimizing the Implementation of SEC-DAEC Codes in FPGAs. - Alfonso Sánchez-Macián; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture. - Jorge A. Martínez 001; Juan Antonio Maestro; Pedro Reviriego (IEEE Comput. Archit. Lett., 2017)

Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016). - Shanshan Liu 001; Pedro Reviriego; Alfonso Sánchez-Macián; Juan Antonio Maestro; Liyi Xiao (Microelectron. Reliab., 2017)

A method to recover critical bits under a double error in SEC-DED protected memories. - Shanshan Liu 001; Pedro Reviriego; Liyi Xiao; Juan Antonio Maestro (Microelectron. Reliab., 2017)

Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection. - Alexis Ramos; Juan Antonio Maestro; Pedro Reviriego (Microelectron. Reliab., 2017)

A method to protect Cuckoo filters from soft errors. - Pedro Reviriego; Salvatore Pontarelli; Juan Antonio Maestro (Microelectron. Reliab., 2017)

Combined Modular Key and Data Error Protection for Content-Addressable Memories. - Alfonso Sánchez-Macián; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Computers, 2017)

Single Event Transient Tolerant Bloom Filter Implementations. - Alfonso Sánchez-Macián; Pedro Reviriego; Juan Antonio Maestro; Shanshan Liu 001 (IEEE Trans. Computers, 2017)

A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes. - Pedro Reviriego; Shanshan Liu 001; Alfonso Sánchez-Macián; Liyi Xiao; Juan Antonio Maestro (IEEE Trans. Reliab., 2017)

Seu and Sefi error detection and correction on a ddr3 memory system. - Ana Cóbreces; Alberto Regadío; Jesús Tabero; Pedro Reviriego; Alfonso Sánchez-Macián; Juan Antonio Maestro (Microelectron. Reliab., 2018)

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes. - Shanshan Liu 001; Pedro Reviriego; Juan Antonio Maestro; Liyi Xiao (Microelectron. Reliab., 2018)

Modular fault tolerant processor architecture on a SoC for space. - Jesús Tabero; Alberto Regadío; César Pérez; Jesús Pazos; Pedro Reviriego; Alfonso Sánchez-Macián; Juan Antonio Maestro (Microelectron. Reliab., 2018)

A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs. - Ricardo Gonzalez-Toral; Pedro Reviriego; Juan Antonio Maestro; Zhen Gao 005 (IEEE Trans. Computers, 2018)

Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. - Alexis Ramos; Anees Ullah; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Computers, 2018)

A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection. - Luis Alberto Aranda; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Efficient Fault-Tolerant Design for Parallel Matched Filters. - Zhen Gao 005; Ming Zhou; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection. - Ricardo Gonzalez-Toral; Shanshan Liu 001; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications. - Zhen Gao 005; Qingqing Jing; Yumeng Li; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2018)

ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs. - Luis Alberto Aranda; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Access, 2019)

Protection Scheme for Star Tracker Images. - Luis Alberto Aranda; Pedro Reviriego; Ricardo Gonzalez-Toral; Juan Antonio Maestro (IEEE Trans. Aerosp. Electron. Syst., 2019)

An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs. - Alexis Ramos; Ricardo Gonzalez-Toral; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Computers, 2019)

Enhancing Instruction TLB Resilience to Soft Errors. - Alfonso Sánchez-Macián; Luis Alberto Aranda; Pedro Reviriego; Vahdaneh Kiani; Juan Antonio Maestro (IEEE Trans. Computers, 2019)

Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes. - Pedro Reviriego; Shanshan Liu 001; Alfonso Sánchez-Macián; Liyi Xiao; Juan Antonio Maestro (DCIS, 2020)

Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation. - Imran Wali; Alfonso Sánchez-Macián; Alexis Ramos; Juan Antonio Maestro (ICECS, 2020)

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications. - Luis Alberto Aranda; Francisco Garcia-Herrero; Luis Esteban; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Access, 2020)

Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA. - Kyle W. Gear; Alfonso Sánchez-Macián; Francisco Garcia-Herrero; Juan Antonio Maestro (Circuits Syst. Signal Process., 2020)

Toward a Fault-Tolerant Star Tracker for Small Satellite Applications. - Luis Alberto Aranda; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Aerosp. Electron. Syst., 2020)

Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase. - Francisco Garcia-Herrero; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Circuits Syst., 2020)

An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform. - Luis Alberto Aranda; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. - Luis Alberto Aranda; Oscar Ruano; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Access, 2021)

Low delay non-binary error correction codes based on Orthogonal Latin Squares. - Francisco Garcia-Herrero; Alfonso Sánchez-Macián; Juan Antonio Maestro (Integr., 2021)

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. - Oscar Ruano; Francisco Garcia-Herrero; Luis Alberto Aranda; Alfonso Sánchez-Macián; Laura Rodriguez; Juan Antonio Maestro (Sensors, 2021)

Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures. - Francisco Garcia-Herrero; Gary McGuire; Mark F. Flanagan; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories. - Francisco Garcia-Herrero; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Emerg. Top. Comput., 2021)

Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. - Yao-Ming Kuo; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (Comput. Electr. Eng., 2022)

ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. - Luis Alberto Aranda; Oscar Ruano; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale. - Alfonso Sánchez-Macián; Alonso Martín-Toledano; Jefferson Andres Bravo-Montes; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Trans. Emerg. Top. Comput., 2022)

An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique. - Kyle W. Gear; Alfonso Sánchez-Macián; Juan Antonio Maestro (Microprocess. Microsystems, 2022)

RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. - Yao-Ming Kuo; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (IEEE Trans. Computers, 2023)

Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. - Yao-Ming Kuo; Mark F. Flanagan; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (IEEE Trans. Aerosp. Electron. Syst., 2023)

Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications. - Daniel Báscones; Francisco Garcia-Herrero; Oscar Ruano; Carlos González 002; Daniel Mozos; Juan Antonio Maestro (IEEE Trans. Computers, 2025)