Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC. - Pierre Plaza; Juan Carlos Diaz; Fermín Calvo; Luis A. Merayo; Maurizio Zamboni; Pietro Scarfone; Marco Barbini (ED&TC, 1995)

A 2.5 Gb/s ATM switch chip set. - Pierre Plaza; Luis A. Merayo; Juan Carlos Diaz; José Luis Conesa (IEEE Trans. Very Large Scale Integr. Syst., 1996)

On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC. - Jacobo Riesco; Juan Carlos Diaz; Luis A. Merayo; José Luis Conesa; Carlos Santos; Eduardo Juárez Martínez (ED&TC, 1997)

ATM Traffic Shaper: ATS. - Juan Carlos Diaz; Pierre Plaza; Jesus Crespo (DATE, 1998)

FPGA Implementation of an ATM Traffic Shaper: ATS (Abstract). - Jesus Crespo; Juan Carlos Diaz; Pimitivo Matas (FPGA, 1998)

The μPP ASIC: design, methodologies and tools for a pay phone system-on-a-chip based on an ARM core and design reuse. - Jacobo Riesco; Juan Carlos Diaz; Pierre Plaza (CICC, 1999)