Juan Fernando Eusse

According to our database, Juan Fernando Eusse authored at least 20 papers between 2009 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs.

Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse

Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020

2019

ASIP algorithmic/architectural co-exploration based on high level performance estimation.

Juan Fernando Eusse Giraldo

PhD thesis, 2019

Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA.

Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse

Integr., 2019

Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs.

Gereon Führ, Seyit Halil Hamurcu, Diego Pala, Thomas Grass, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse

IEEE Embed. Syst. Lett., 2019

2017

MAPS: A Software Development Environment for Embedded Multicore Applications.

Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng

Proceedings of the Handbook of Hardware/Software Codesign., 2017

Towards Parallelism Extraction for Heterogeneous Multicore Android Devices.

Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma

Int. J. Parallel Program., 2017

Extraction of recursion level parallelism for embedded multicore systems.

Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016

Concurrent memory subsystem and application optimization for ASIP design.

Juan Fernando Eusse, Francisco Fernandez, Rainer Leupers, Gerd Ascheid

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

2015

CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design.

Juan Fernando Eusse Giraldo, Christopher Williams, Rainer Leupers

ACM Trans. Reconfigurable Technol. Syst., 2015

Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation.

Juan Fernando Eusse, Luis Gabriel Murillo, Christopher McGirr, Rainer Leupers, Gerd Ascheid

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Parallelism extraction in embedded software for android devices.

Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Extraction of Kahn Process Networks from While Loops in Embedded Software.

Miguel Angel Aguilar, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Maximilian Odendahl

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014

Pre-architectural performance estimation for ASIP design based on abstract processor models.

Juan Fernando Eusse Giraldo, Christopher Williams, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A flexible ASIP architecture for connected components labeling in embedded vision applications.

Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012

A Protein Sequence Analysis Hardware Accelerator Based on Divergences.

Juan Fernando Eusse Giraldo, Nahri Moreano, Alba Cristina Magalhaes Alves de Melo, Ricardo Pezzuol Jacobi

Int. J. Reconfigurable Comput., 2012

Hybrid simulation for extensible processor cores.

Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Synchronization for hybrid MPSoC full-system simulation.

Luis Gabriel Murillo, Juan Fernando Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010

A HMMER hardware accelerator using divergences.

Juan Fernando Eusse Giraldo, Nahri Moreano, Ricardo Pezzuol Jacobi, Alba Cristina Magalhaes Alves de Melo

Proceedings of the Design, Automation and Test in Europe, 2010

2009

BRICK: a multi-context expression grained reconfigurable architecture.

Juan Fernando Eusse Giraldo, Michael Hübner, Ricardo Pezzuol Jacobi

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Signal Processing Domain Application Mapping on the Brick Reconfigurable Array.

Juan Fernando Eusse Giraldo, Ricardo Pezzuol Jacobi

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009