Signal Processing Domain Application Mapping on the Brick Reconfigurable Array. - Juan Fernando Eusse Giraldo; Ricardo Pezzuol Jacobi (ReConFig, 2009)

BRICK: a multi-context expression grained reconfigurable architecture. - Juan Fernando Eusse Giraldo; Michael Hübner 001; Ricardo Pezzuol Jacobi (SBCCI, 2009)

A HMMER hardware accelerator using divergences. - Juan Fernando Eusse Giraldo; Nahri Moreano; Ricardo Pezzuol Jacobi; Alba Cristina Magalhaes Alves de Melo (DATE, 2010)

Synchronization for hybrid MPSoC full-system simulation. - Luis Gabriel Murillo; Juan Fernando Eusse; Jovana Jovic; Sergey Yakoushkin; Rainer Leupers; Gerd Ascheid (DAC, 2012)

Hybrid simulation for extensible processor cores. - Jovana Jovic; Sergey Yakoushkin; Luis Gabriel Murillo; Juan Fernando Eusse; Rainer Leupers; Gerd Ascheid (DATE, 2012)

A Protein Sequence Analysis Hardware Accelerator Based on Divergences. - Juan Fernando Eusse Giraldo; Nahri Moreano; Alba Cristina Magalhaes Alves de Melo; Ricardo Pezzuol Jacobi (Int. J. Reconfigurable Comput., 2012)

A flexible ASIP architecture for connected components labeling in embedded vision applications. - Juan Fernando Eusse; Rainer Leupers; Gerd Ascheid; Patrick Sudowe; Bastian Leibe; Tamon Sadasue (DATE, 2014)

Pre-architectural performance estimation for ASIP design based on abstract processor models. - Juan Fernando Eusse Giraldo; Christopher Williams 004; Luis Gabriel Murillo; Rainer Leupers; Gerd Ascheid (ICSAMOS, 2014)

Extraction of Kahn Process Networks from While Loops in Embedded Software. - Miguel Angel Aguilar; Juan Fernando Eusse; Rainer Leupers; Gerd Ascheid; Maximilian Odendahl (HPCC/CSS/ICESS, 2015)

Parallelism extraction in embedded software for android devices. - Miguel Angel Aguilar; Juan Fernando Eusse; Projjol Ray; Rainer Leupers; Gerd Ascheid; Weihua Sheng; Prashant Sharma (SAMOS, 2015)

Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation. - Juan Fernando Eusse; Luis Gabriel Murillo; Christopher McGirr; Rainer Leupers; Gerd Ascheid (SCOPES, 2015)

CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design. - Juan Fernando Eusse Giraldo; Christopher Williams 004; Rainer Leupers (ACM Trans. Reconfigurable Technol. Syst., 2015)

Concurrent memory subsystem and application optimization for ASIP design. - Juan Fernando Eusse; Francisco Fernandez; Rainer Leupers; Gerd Ascheid (SAMOS, 2016)

Extraction of recursion level parallelism for embedded multicore systems. - Miguel Angel Aguilar; Rainer Leupers; Gerd Ascheid; Juan Fernando Eusse (SAMOS, 2017)

Towards Parallelism Extraction for Heterogeneous Multicore Android Devices. - Miguel Angel Aguilar; Juan Fernando Eusse; Projjol Ray; Rainer Leupers; Gerd Ascheid; Weihua Sheng; Prashant Sharma (Int. J. Parallel Program., 2017)

MAPS: A Software Development Environment for Embedded Multicore Applications. - Rainer Leupers; Miguel Angel Aguilar; Juan Fernando Eusse; Jerónimo Castrillón; Weihua Sheng (Handbook of Hardware/Software Codesign, 2017)

Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs. - Gereon Führ; Seyit Halil Hamurcu; Diego Pala; Thomas Grass; Rainer Leupers; Gerd Ascheid; Juan Fernando Eusse (IEEE Embed. Syst. Lett., 2019)

Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. - Gereon Führ; Ahmed Hallawa; Rainer Leupers; Gerd Ascheid; Juan Fernando Eusse (Integr., 2019)

ASIP algorithmic/architectural co-exploration based on high level performance estimation. - Juan Fernando Eusse Giraldo (2019)

3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs. - Gereon Führ; Ahmed Hallawa; Rainer Leupers; Gerd Ascheid; Juan Fernando Eusse (ARCS, 2020)