Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. - Juan M. Cebrian; Juan L. Aragón; José M. García 001; Stefanos Kaxiras (Conf. Computing Frontiers, 2007)

Leakage Energy Reduction in Value Predictors through Static Decay. - Juan M. Cebrian; Juan L. Aragón; José M. García 001 (IPDPS, 2007)

Efficient microarchitecture policies for accurately adapting to power constraints. - Juan M. Cebrian; Juan L. Aragón; José M. García 001; Pavlos Petoumenos; Stefanos Kaxiras (IPDPS, 2009)

MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance. - Pavlos Petoumenos; Georgia Psychou; Stefanos Kaxiras; Juan Manuel Cebrian Gonzalez; Juan L. Aragón (ARCS, 2010)

Token3D: Reducing Temperature in 3D Die-Stacked CMPs through Cycle-Level Power Control Mechanisms. - Juan M. Cebrian; Juan L. Aragón; Stefanos Kaxiras (Euro-Par (1), 2011)

Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads. - Juan M. Cebrian; Juan L. Aragón; Stefanos Kaxiras (IPDPS, 2011)

Leakage-efficient design of value predictors through state and non-state preserving techniques. - Juan M. Cebrian; Juan L. Aragón; José M. García 001; Stefanos Kaxiras (J. Supercomput., 2011)

Energy Efficiency Analysis of GPUs. - Juan M. Cebrian; Ginés D. Guerrero; José M. García 001 (IPDPS Workshops, 2012)

Improving Energy Efficiency through Parallelization and Vectorization on Intel Core i5 and i7 Processors. - Juan M. Cebrian; Lasse Natvig; Jan Christian Meyer (SC Companion, 2012)

Temperature effects on on-chip energy measurements. - Juan M. Cebrian; Lasse Natvig (IGCC, 2013)

Energy-Efficient Sparse Matrix Autotuning with CSX - A Trade-off Study. - Jan Christian Meyer; Juan M. Cebrian; Lasse Natvig; Vasileios Karakasis; Dimitris Siakavaras; Konstantinos Nikas (IPDPS Workshops, 2013)

Efficient inter-core power and thermal balancing for multicore processors. - Juan M. Cebrian; Daniel Sánchez 004; Juan L. Aragón; Stefanos Kaxiras (Computing, 2013)

Modeling the impact of permanent faults in caches. - Daniel Sánchez 004; Yiannakis Sazeides; Juan M. Cebrian; José M. García 001; Juan L. Aragón (ACM Trans. Archit. Code Optim., 2013)

Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks. - Juan M. Cebrian; Magnus Jahre; Lasse Natvig (ISPASS, 2014)

Performance and energy impact of parallelization and vectorization techniques in modern microprocessors. - Juan M. Cebrian; Lasse Natvig; Jan Christian Meyer (Computing, 2014)

Toward energy efficiency in heterogeneous processors: findings on virtual screening methods. - Ginés D. Guerrero; Juan M. Cebrian; Horacio Emilio Pérez Sánchez; José M. García 001; Manuel Ujaldon; José M. Cecilia (Concurr. Comput. Pract. Exp., 2014)

Managing power constraints in a single-core scenario through power tokens. - Juan M. Cebrian; Daniel Sánchez 004; Juan L. Aragón; Stefanos Kaxiras (J. Supercomput., 2014)

Early Experiences with Separate Caches for Private and Shared Data. - Juan M. Cebrian; Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio (e-Science, 2015)

V-PFORDelta: Data Compression for Energy Efficient Computation of Time Series. - Abdullah Al Hasib; Juan M. Cebrian; Lasse Natvig (HiPC, 2015)

Evaluation of 3-D Stencil Codes on the Intel Xeon Phi Coprocessor. - Mario Hernández; Juan M. Cebrian; José M. Cecilia; José M. García 001 (PARCO, 2015)

Evaluation of the 3-D finite difference implementation of the acoustic diffusion equation model on massively parallel architectures. - Mario Hernández; Baldomero Imbernón; Juan M. Navarro; José M. García 001; Juan M. Cebrian; José M. Cecilia (Comput. Electr. Eng., 2015)

ParVec: vectorizing the PARSEC benchmark suite. - Juan M. Cebrian; Magnus Jahre; Lasse Natvig (Computing, 2015)

Soft-error mitigation by means of decoupled transactional memory threads. - Daniel Sánchez 004; Juan M. Cebrian; José M. García 001; Juan L. Aragón (Distributed Comput., 2015)

Transient Temperature Prediction for Aging Thermal Sensors Using Artificial Neural Network. - Kameswar Rao Vaddina; Juan M. Cebrian; Lasse Natvig (PDP, 2016)

Code modernization strategies to 3-D Stencil-based applications on Intel Xeon Phi: KNC and KNL. - Juan M. Cebrian; José M. Cecilia; Mario Hernández; José M. García 001 (Comput. Math. Appl., 2017)

A dedicated private-shared cache design for scalable multiprocessors. - Juan M. Cebrian; Ricardo Fernández-Pascual; Alexandra Jimborean; Manuel E. Acacio; Alberto Ros 001 (Concurr. Comput. Pract. Exp., 2017)

Stencil codes on a vector length agnostic architecture. - Adrià Armejach; Helena Caminal; Juan M. Cebrian; Rekai González-Alberquilla; Chris Adeniyi-Jones; Mateo Valero; Marc Casas; Miquel Moretó (PACT, 2018)

Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. - Helena Caminal; Diego Caballero; Juan M. Cebrian; Roger Ferrer; Marc Casas; Miquel Moretó; Xavier Martorell; Mateo Valero (J. Supercomput., 2018)

A vectorized k-means algorithm for compressed datasets: design and experimental analysis. - Abdullah Al Hasib; Juan M. Cebrian; Lasse Natvig (J. Supercomput., 2018)

POSTER: An Optimized Predication Execution for SIMD Extensions. - Adrián Barredo; Juan M. Cebrian; Miquel Moretó; Marc Casas; Mateo Valero (PACT, 2019)

Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. - Adrián Barredo; Juan M. Cebrian; Miquel Moretó; Marc Casas; Mateo Valero (HPCA, 2020)

Boosting Store Buffer Efficiency with Store-Prefetch Bursts. - Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (MICRO, 2020)

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. - Juan M. Cebrian; Adrián Barredo; Helena Caminal; Miquel Moretó; Marc Casas; Mateo Valero (Future Gener. Comput. Syst., 2020)

High-throughput fuzzy clustering on heterogeneous architectures. - Juan M. Cebrian; Baldomero Imbernón; Jesús A. Soto; José M. García 001; José M. Cecilia (Future Gener. Comput. Syst., 2020)

Offloading strategies for Stencil kernels on the KNC Xeon Phi architecture: Accuracy versus performance. - Mario Hernández; Juan M. Cebrian; José M. Cecilia; José M. García 001 (Int. J. High Perform. Comput. Appl., 2020)

Using Arm's scalable vector extension on stencil codes. - Adrià Armejach; Helena Caminal; Juan M. Cebrian; Rubén Langarita; Rekai González-Alberquilla; Chris Adeniyi-Jones; Mateo Valero; Marc Casas; Miquel Moretó (J. Supercomput., 2020)

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. - Adrián Barredo; Juan M. Cebrian; Mateo Valero; Marc Casas; Miquel Moretó (J. Supercomput., 2020)

Scalability analysis of AVX-512 extensions. - Juan M. Cebrian; Lasse Natvig; Magnus Jahre (J. Supercomput., 2020)

Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations. - Eduardo José Gómez-Hernández; Juan M. Cebrian; J. Rubén Titos Gil; Stefanos Kaxiras; Alberto Ros 001 (MICRO, 2021)

Splash-4: A Modern Benchmark Suite with Lock-Free Constructs. - Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (IISWC, 2022)

Free atomics: hardware atomic operations without fences. - Ashkan Asgharzadeh; Juan M. Cebrian; Arthur Perais; Stefanos Kaxiras; Alberto Ros 001 (ISCA, 2022)

Compiler-Assisted Compaction/Restoration of SIMD Instructions. - Juan M. Cebrian; Thibaud Balem; Adrián Barredo; Marc Casas; Miquel Moretó; Alberto Ros 001; Alexandra Jimborean (IEEE Trans. Parallel Distributed Syst., 2022)

Near-optimal multi-accelerator architectures for predictive maintenance at the edge. - Mostafa Koraei; Juan M. Cebrian; Magnus Jahre (Future Gener. Comput. Syst., 2023)

Bounding Speculative Execution of Atomic Regions to a Single Retry. - Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (ASPLOS (4), 2024)

Hardware Cache Locking for All Memory Updates. - Ashkan Asgharzadeh; Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (ICCD, 2024)

Temporarily Unauthorized Stores: Write First, Ask for Permission Later. - Juan M. Cebrian; Magnus Jahre; Alberto Ros 001 (MICRO, 2024)

Precise characterization of coherence activity in multicores using gem5. - Joaquín Ferrer; Juan M. Cebrian; Ricardo Fernández-Pascual; Manuel E. Acacio (J. Supercomput., 2025)