Design Guides for a Correct DC Operation in RTD-based Threshold Gates. - José M. Quintana; Maria J. Avedillo; Juan Núñez 002 (DSD, 2006)

Limits to a Correct Evaluation in RTD-based Ternary Inverters. - Juan Núñez 002; José M. Quintana; Maria José Avedillo (ICECS, 2006)

Correct operation in SMOBILE-based quasi-differential quantizers. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ECCTD, 2007)

Operation limits in RTD-based ternary quantizers. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ACM Great Lakes Symposium on VLSI, 2007)

Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ISMVL, 2007)

A quasi-differential quantizer based on SMOBILE. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (SBCCI, 2007)

Limits to a correct operation in RTD-based ternary inverters. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ISCAS, 2008)

Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. - Juan Núñez 002; José M. Quintana; Maria J. Avedillo (ISCAS, 2009)

Operation Limits for RTD-Based MOBILE Circuits. - José M. Quintana; Maria J. Avedillo; Juan Núñez 002; Héctor Pettenghi (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Evaluation of RTD-CMOS Logic Gates. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (DSD, 2010)

Single phase MOS-NDR mobile networks. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (ISCAS, 2010)

Efficient realization of RTD-CMOS logic gates. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (ACM Great Lakes Symposium on VLSI, 2011)

Bifurcation diagrams in MOS-NDR frequency divider circuits. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (ICECS, 2012)

Compact and Power Efficient MOS-NDR Muller C-Elements. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (DoCEIS, 2012)

Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (PATMOS, 2012)

Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (DSD, 2013)

Novel pipeline architectures based on Negative Differential Resistance devices. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (Microelectron. J., 2013)

DOE based high-performance gate-level pipelines. - Juan Núñez 002; Maria J. Avedillo; Hector J. Quintero (PATMOS, 2014)

Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. - Juan Núñez 002; Maria J. Avedillo; José M. Quintana (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. - Juan Núñez 002; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (LASCAS, 2015)

Impact of pipeline in the power performance of tunnel transistor circuits. - Maria J. Avedillo; Juan Núñez 002 (PATMOS, 2016)

Secure cryptographic hardware implementation issues for high-performance applications. - Erica Tena-Sánchez; Antonio J. Acosta 001; Juan Núñez 002 (PATMOS, 2016)

Exploring logic architectures suitable for TFETs devices. - Juan Núñez 002; Maria J. Avedillo (ISCAS, 2017)

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. - Erica Tena-Sánchez; Ignacio M. Delgado-Lozano; Juan Núñez 002; Antonio J. Acosta 001 (DCIS, 2018)

All-inversion region gm/ID methodology for RF circuits in FinFET technologies. - Rafaella Fiorelli; Juan Núñez 002; Fernando Silveira (NEWCAS, 2018)

Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. - Hector J. Quintero; Manuel Jiménez Través; Maria J. Avedillo; Juan Núñez 002 (SMACD, 2018)

Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. - Pablo Saraza-Canflanca; D. Malagon; Fábio Passos; A. Toro; Juan Núñez 002; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2018)

Impact of the RT-level architecture on the power performance of tunnel transistor circuits. - Maria J. Avedillo; Juan Núñez 002 (Int. J. Circuit Theory Appl., 2018)

An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. - Pablo Martín-Lloret; Juan Núñez 002; Elisenda Roca; Rafael Castro-López; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2019)

Experimental Characterization of Time-Dependent Variability in Ring Oscillators. - Juan Núñez 002; Elisenda Roca; Rafael Castro-López; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2019)

Power and Speed Evaluation of Hyper-FET Circuits. - Juan Núñez 002; Maria J. Avedillo (IEEE Access, 2019)

Emerging technologies and computing paradigms for the Internet of Everything applications. International Journal of Circuit, Theory, and Applications. - Aida Todri-Sanial; Xueqing Li 002; Juan Núñez 002 (Int. J. Circuit Theory Appl., 2019)

An Approach to the Device-Circuit Co-Design of HyperFET Circuits. - Manuel Jiménez Través; Juan Núñez 002; Maria José Avedillo (ISCAS, 2020)

Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

Insights Into the Dynamics of Coupled VO2 Oscillators for ONNs. - Juan Núñez 002; José M. Quintana; Maria José Avedillo; Manuel Jiménez Través; Aida Todri-Sanial; Elisabetta Corti; Siegfried F. Karg; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (IEEE Trans. Emerg. Top. Comput., 2021)

Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. - Manuel Jiménez Través; Maria José Avedillo; Juan Núñez 002; Bernabé Linares-Barranco (DCIS, 2022)

Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications. - Juan Núñez 002; Simon Thomann; Hussam Amrouch; Maria J. Avedillo (ICECS 2022, 2022)

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. - Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez 002; Antonio J. Acosta 001 (IEEE Embed. Syst. Lett., 2022)

How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. - Aida Todri-Sanial; Stefania Carapezzi; Corentin Delacour; Madeleine Abernot; Thierry Gil; Elisabetta Corti; Siegfried F. Karg; Juan Núñez 002; Manuel Jiménez Través; Maria J. Avedillo; Bernabé Linares-Barranco (IEEE Trans. Neural Networks Learn. Syst., 2022)

Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. - Victor M. van Santen; Jose M. Gata-Romero; Juan Núñez 002; Rafael Castro-López; Elisenda Roca; Hussam Amrouch (IRPS, 2023)

Reliability evaluation of IC Ring Oscillator PUFs. - Jose M. Gata-Romero; Elisenda Roca; Juan Núñez 002; Rafael Castro-López; Francisco V. Fernández 001 (SMACD, 2023)

Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. - Juan Núñez 002; Maria J. Avedillo; Manuel Jiménez Través (SMACD, 2023)

Operating Coupled VO₂-Based Oscillators for Solving Ising Models. - Maria J. Avedillo; Manuel Jiménez Través; Corentin Delacour; Aida Todri-Sanial; Bernabé Linares-Barranco; Juan Núñez 002 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)