Empirical evaluation of timing and power in resonant clock distribution. - Juang-Ying Chueh; Conrad H. Ziesler; Marios C. Papaefthymiou (ISCAS (2), 2004)

Experimental Evaluation of Resonant Clock Distribution. - Juang-Ying Chueh; Conrad H. Ziesler; Marios C. Papaefthymiou (ISVLSI, 2004)

Fast, efficient, recovering, and irreversible. - Visvesh S. Sathe 001; Juang-Ying Chueh; Joohee Kim; Conrad H. Ziesler; Suhwan Kim 001; Marios C. Papaefthymiou (Conf. Computing Frontiers, 2005)

Two-Phase Resonant Clock Distribution. - Juang-Ying Chueh; Marios C. Papaefthymiou; Conrad H. Ziesler (ISVLSI, 2005)

900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. - Juang-Ying Chueh; Visvesh S. Sathe 001; Marios C. Papaefthymiou (CICC, 2006)

A 1.1ghz charge-recovery logic. - Visvesh S. Sathe 001; Juang-Ying Chueh; Marios Papaefthymio (ISSCC, 2006)

Energy-Efficient GHz-Class Charge-Recovery Logic. - Visvesh S. Sathe 001; Juang-Ying Chueh; Marios C. Papaefthymiou (IEEE J. Solid State Circuits, 2007)

Efficient standard cell abutment checker. - Juang-Ying Chueh; Chuck Tung (ICECS, 2013)

Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns. - Nicky Lu; Chun Shiah; Juang-Ying Chueh; Bor-Doou Rong; Wei-Jr Huang; Ho-Yin Chen; Cheng-Nan Chang; Chia-Wei Chang; Tzung-Shen Chen (VLSI Circuits, 2021)