Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks Simulation. - Juanjo Noguera; Rosa M. Badia; Jordi Domingo-Pascual; Josep Solé-Pareta (EUROMICRO, 1999)

A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation. - Juanjo Noguera; Rosa M. Badia; Jordi Domingo-Pascual; Josep Solé-Pareta (FPL, 1999)

Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers. - Juanjo Noguera; Rosa M. Badia (FPL, 2000)

Modelling and Performance Evaluation of a National Scale Switchless Based Network. - Josep Solé-Pareta; Davide Careglio; Salvatore Spadaro; Jaume Masip-Torné; Juanjo Noguera; Gabriel Junyent (INTERWORKING, 2000)

Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures. - Juanjo Noguera; Rosa M. Badia (ISSS, 2000)

A HW/SW partitioning algorithm for dynamically reconfigurable architectures. - Juanjo Noguera; Rosa M. Badia (DATE, 2001)

Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. - Juanjo Noguera; Rosa M. Badia (CODES, 2002)

HW/SW codesign techniques for dynamically reconfigurable architectures. - Juanjo Noguera; Rosa M. Badia (IEEE Trans. Very Large Scale Integr. Syst., 2002)

System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. - Juanjo Noguera; Rosa M. Badia (CASES, 2003)

Power-performance trade-offs for reconfigurable computing. - Juanjo Noguera; Rosa M. Badia (CODES+ISSS, 2004)

Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. - Juanjo Noguera; Rosa M. Badia (ACM Trans. Embed. Comput. Syst., 2004)

Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures. - Zexin Pan; Juanjo Noguera; B. Earl Wells (ERSA, 2005)

Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures. - Juanjo Noguera; Rosa M. Badia (FPL, 2005)

Software-friendly HW/SW co-simulation: an industrial case study. - Juanjo Noguera; Luis Baldez; Narcis Simon; Lluis Abello (DATE Designers' Forum, 2006)

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Juanjo Noguera; Nikil D. Dutt (FPT, 2006)

System-level power-performance tradeoffs for reconfigurable computing. - Juanjo Noguera; Rosa M. Badia (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Nikil D. Dutt; Juanjo Noguera (DAC, 2007)

Power Reduction in Network Equipment through Adaptive Partial Reconfiguration. - Juanjo Noguera; Irwin O. Kennedy (FPL, 2007)

Towards Novel Approaches in Design Automation for FPGA Power Optimization. - Juanjo Noguera; Robert Esser; Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001 (PATMOS, 2008)

Generic Software Framework for Adaptive Applications on FPGAs. - Suhaib A. Fahmy; Jorg Lotze; Juanjo Noguera; Linda Doyle; Robert Esser (FCCM, 2009)

Development Framework for Implementing FPGA-Based Cognitive Network Nodes. - Jorg Lotze; Suhaib A. Fahmy; Juanjo Noguera; Baris Özgül; Linda Doyle; Robert Esser (GLOBECOM, 2009)

Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds. - Paul D. Sutton; Jörg Lotze; Hicham Lahlou; Baris Özgül; Suhaib A. Fahmy; Keith E. Nolan; Juanjo Noguera; Linda E. Doyle (CrownCom, 2010)

Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. - Michael Hübner 001; Diana Göhringer; Juanjo Noguera; Jürgen Becker 001 (IPDPS Workshops, 2010)

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. - Michael Hübner 001; Joachim Meyer 001; Oliver Sander; Lars Braun; Jürgen Becker 001; Juanjo Noguera; Rodney Stewart (ISVLSI, 2010)

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration. - Joachim Meyer 001; Michael Hübner 001; Lars Braun; Oliver Sander; Juanjo Noguera; Rodney Stewart; Jürgen Becker 001 (ISVLSI (Selected papers), 2010)

Iris: an architecture for cognitive radio networking testbeds. - Paul D. Sutton; Jörg Lotze; Hicham Lahlou; Suhaib A. Fahmy; Keith E. Nolan; Baris Özgül; Thomas W. Rondeau; Juanjo Noguera; Linda Doyle (IEEE Commun. Mag., 2010)

Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. - Sudarshan Banerjee; Elaheh Bozorgzadeh; Juanjo Noguera; Nikil D. Dutt (ACM Trans. Reconfigurable Technol. Syst., 2010)

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. - Joachim Meyer 001; Juanjo Noguera; Michael Hübner 001; Lars Braun; Oliver Sander; R. M. Gil; Rodney Stewart; Jürgen Becker 001 (DATE, 2011)

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools. - Kees A. Vissers; Stephen Neuendorffer; Juanjo Noguera (DATE, 2011)

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs. - Joachim Meyer 001; Juanjo Noguera; Michael Hübner 001; Rodney Stewart; Jürgen Becker 001 (FPL, 2011)

A Model-Based Approach to Cognitive Radio Design. - Jorg Lotze; Suhaib A. Fahmy; Juanjo Noguera; Linda Doyle (IEEE J. Sel. Areas Commun., 2011)

High-Level Synthesis for FPGAs: From Prototyping to Deployment. - Jason Cong; Bin Liu 006; Stephen Neuendorffer; Juanjo Noguera; Kees A. Vissers; Zhiru Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq. - Antonio Filgueras; Eduard Gil; Carlos Álvarez 001; Daniel Jiménez-González; Xavier Martorell; Jan Langer; Juanjo Noguera (VLSI-SoC, 2013)

Software-programmable digital pre-distortion on the Zynq SoC. - Baris Özgül; Jan Langer; Juanjo Noguera; Kees A. Vissers (VLSI-SoC, 2013)

OmpSs@Zynq all-programmable SoC ecosystem. - Antonio Filgueras; Eduard Gil; Daniel Jiménez-González; Carlos Álvarez 001; Xavier Martorell; Jan Langer; Juanjo Noguera; Kees A. Vissers (FPGA, 2014)

Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC. - Daniel Jiménez-González; Carlos Álvarez 001; Antonio Filgueras; Xavier Martorell; Jan Langer; Juanjo Noguera; Kees A. Vissers (CoRR, 2015)

Xilinx First 7nm Device: Versal AI Core (VC1902). - Sagheer Ahmad; Sridhar Subramanian; Vamsi Boppana; Shankar Lakka; Fu-Hing Ho; Tomai Knopp; Juanjo Noguera; Gaurav Singh; Ralph Wittig (Hot Chips Symposium, 2019)

AMD XDNA NPU in Ryzen AI Processors. - Alejandro Rico; Satyaprakash Pareek; Javier Cabezas; David Clarke; Baris Özgül; Francisco Barat; Yao Fu; Stephan Münz; Dylan Stuart; Patrick Schlangen; Pedro Duarte; Sneha Date; et al. (IEEE Micro, 2024)