Detection of Cerebral Aneurysm by Performing Thresholding-Spatial Filtering-Thresholding Operations on Digital Subtraction Angiogram. - Jubin Mitra; Abhijit Chandra (ACITY (2), 2012)

Reconfigurable Concurrent VLSI (FPGA) Design Architecture of CRC-32 for High-Speed Data Communication. - Jubin Mitra; Tapan Kumar Nayak (iNIS, 2015)

Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment. - Jubin Mitra; Shuaib Ahmad Khan; Rourab Paul; Sanjoy Mukherjee; Amlan Chakrabarti; Tapan Kumar Nayak (VLSID, 2016)

Reconfigurable very high throughput low latency VLSI (FPGA) design architecture of CRC 32. - Jubin Mitra; Tapan Kumar Nayak (Integr., 2017)

An FPGA-Based Phase Measurement System. - Jubin Mitra; Tapan Kumar Nayak (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Development of FPGA based phase alignment logic for the high speed protocol in HEP Experiments. - Shuaib Ahmad Khan; Jubin Mitra; Tapan Kumar Nayak (Comput. Phys. Commun., 2021)