A smart random code injection to mask power analysis based side channel attacks. - Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (CODES+ISSS, 2007)

RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. - Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (DAC, 2007)

MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. - Jude Angelo Ambrose; Sri Parameswaran; Aleksandar Ignjatovic (ICCAD, 2008)

Anatomy of Differential Power Analysis for AES. - Jude Angelo Ambrose; Naeill Aldon; Aleksandar Ignjatovic; Sri Parameswaran (SYNASC, 2008)

Power analysis side channel attacks: the processor design-level context. - Jude Angelo Ambrose (2009)

RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. - Roshan G. Ragel; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran (DIPES/BICC, 2010)

Composability and Predictability for Independent Application Development, Verification, and Execution. - Benny Akesson; Anca Mariana Molnos; Andreas Hansson 001; Jude Angelo Ambrose; Kees Goossens (Multiprocessor System-on-Chip, 2011)

Composable local memory organisation for streaming applications on embedded MPSoCs. - Jude Angelo Ambrose; Anca Mariana Molnos; Andrew Nelson 001; Sorin Cotofana; Kees Goossens; Ben H. H. Juurlink (Conf. Computing Frontiers, 2011)

Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks. - Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran; Aleksandar Ignjatovic (IET Comput. Digit. Tech., 2011)

Design and implementation of an operating system for composable processor sharing. - Andreas Hansson 001; Marcus Ekerhult; Anca Mariana Molnos; Aleksandar Milutinovic; Andrew Nelson 001; Jude Angelo Ambrose; Kees Goossens (Microprocess. Microsystems, 2011)

Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. - Héctor Pettenghi; Leonel Sousa; Jude Angelo Ambrose (ASP-DAC, 2012)

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. - Mohammad Shihabul Haque; Roshan G. Ragel; Jude Angelo Ambrose; Swarnalatha Radhakrishnan; Sri Parameswaran (CODES+ISSS, 2012)

A TDM NoC supporting QoS, multicast, and fast connection set-up. - Radu Andrei Stefan; Anca Mariana Molnos; Jude Angelo Ambrose; Kees Goossens (DATE, 2012)

Fine-grained hardware/software methodology for process migration in MPSoCs. - Tuo Li 001; Jude Angelo Ambrose; Sri Parameswaran (ICCAD, 2012)

CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study. - Jude Angelo Ambrose; Aleksandar Ignjatovic; Sri Parameswaran (ISCAS, 2012)

Randomized Instruction Injection to Counter Power Analysis Attacks. - Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (ACM Trans. Embed. Comput. Syst., 2012)

DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. - Jude Angelo Ambrose; Héctor Pettenghi; Leonel Sousa (ASP-DAC, 2013)

RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. - Tuo Li 001; Muhammad Shafique 001; Jude Angelo Ambrose; Semeen Rehman; Jörg Henkel; Sri Parameswaran (DAC, 2013)

Reconfigurable pipelined coprocessor for multi-mode communication transmission. - Liang Tang; Jude Angelo Ambrose; Sri Parameswaran (DAC, 2013)

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. - Tuo Li 001; Muhammad Shafique 001; Semeen Rehman; Swarnalatha Radhakrishnan; Roshan G. Ragel; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (DATE, 2013)

DRMA: dynamically reconfigurable MPSoC architecture. - Lawrance Zhang; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran; Roshan G. Ragel; Swarnalatha Radhakrishnan; Kewal K. Saluja (ACM Great Lakes Symposium on VLSI, 2013)

DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. - Tuo Li 001; Muhammad Shafique 001; Semeen Rehman; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (ICCAD, 2013)

Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs. - Jude Angelo Ambrose; Isuru Nawinne; Sri Parameswaran (ISCAS, 2013)

Variable increment step based reconfigurable interleaver for multimode communication application. - Liang Tang; Jude Angelo Ambrose; Sri Parameswaran (ISCAS, 2013)

A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. - Ankita Arora; Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran (ISVLSI, 2013)

A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. - Roshan G. Ragel; Swarnalatha Radhakrishnan; Jude Angelo Ambrose; Sri Parameswaran (VLSI Design, 2013)

MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping. - Liang Tang; Jude Angelo Ambrose; Sri Parameswaran (VLSI Design, 2013)

Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks. - Jude Angelo Ambrose; Héctor Pettenghi; Darshana Jayasinghe; Leonel Sousa (IET Circuits Devices Syst., 2013)

SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. - Jude Angelo Ambrose; Jorgen Peddersen; Sri Parameswaran; Alvin Labios; Yusuke Yachide (ASP-DAC, 2014)

Advanced modes in AES: Are they safe from power analysis based side channel attacks? - Darshana Jayasinghe; Roshan G. Ragel; Jude Angelo Ambrose; Aleksandar Ignjatovic; Sri Parameswaran (ICCD, 2014)

Method for designing multi-channel RNS architectures to prevent power analysis SCA. - Héctor Pettenghi; Jude Angelo Ambrose; Ricardo Chaves; Leonel Sousa (ISCAS, 2014)

Improving GA-Based NoC Mapping Algorithms Using a Formal Model. - Vinitha Arakkonam Palaniveloo; Jude Angelo Ambrose; Arcot Sowmya (ISVLSI, 2014)

Reconfigurable Convolutional Codec for Physical Layer Communication Security Application. - Liang Tang; Jude Angelo Ambrose; Sri Parameswaran; Sha Zhu (MILCOM, 2014)

Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study. - Roshan G. Ragel; Swarnalatha Radhakrishnan; Jude Angelo Ambrose (CoRR, 2014)

ADAPT: An adaptive manycore methodology for software pipelined applications. - Xi Zhang 003; Haris Javaid; Muhammad Shafique 001; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (ASP-DAC, 2015)

QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks. - Darshana Jayasinghe; Aleksandar Ignjatovic; Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (CASES, 2015)

Dynamic reconfigurable puncturing for secure wireless communication. - Liang Tang; Jude Angelo Ambrose; Akash Kumar 001; Sri Parameswaran (DATE, 2015)

Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. - Jude Angelo Ambrose; Yusuke Yachide; Kapil Batra; Jorgen Peddersen; Sri Parameswaran (ICCD, 2015)

ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. - Jude Angelo Ambrose; Nick Higgins; Mrinal Chakravarthy; Shivam Gargg; Tuo Li 001; Daniel Murphy; Aleksandar Ignjatovic; Sri Parameswaran (ISCAS, 2015)

Side channel attacks in embedded systems: A tale of hostilities and deterrence. - Jude Angelo Ambrose; Roshan G. Ragel; Darshana Jayasinghe; Tuo Li 001; Sri Parameswaran (ISQED, 2015)

ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. - Jude Angelo Ambrose; Tuo Li 001; Daniel Murphy; Shivam Gargg; Nick Higgins; Sri Parameswaran (VLSID, 2015)

SecureD: A Secure Dual Core Embedded Processor. - Roshan G. Ragel; Jude Angelo Ambrose; Sri Parameswaran (CoRR, 2015)

RECORD: Reducing register traffic for checkpointing in embedded processors. - Tuo Li 001; Jude Angelo Ambrose; Sri Parameswaran (DATE, 2016)

Processor Design for Soft Errors: Challenges and State of the Art. - Tuo Li 001; Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (ACM Comput. Surv., 2016)

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. - Tuo Li 001; Muhammad Shafique 001; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (IEEE Trans. Computers, 2017)

QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks. - Darshana Jayasinghe; Aleksandar Ignjatovic; Roshan G. Ragel; Jude Angelo Ambrose; Sri Parameswaran (ACM Trans. Design Autom. Electr. Syst., 2021)