SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference. - Jude Haris; Perry Gibson; José Cano 001; Nicolas Bohm Agostini; David R. Kaeli (SBAC-PAD, 2021)

SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference. - Jude Haris; Perry Gibson; José Cano 001; Nicolas Bohm Agostini; David R. Kaeli (J. Parallel Distributed Comput., 2023)

AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators. - Nicolas Bohm Agostini; Jude Haris; Perry Gibson; Malith Jayaweera; Norm Rubin; Antonino Tumeo; José L. Abellán; José Cano 001; David R. Kaeli (CGO, 2024)

Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR. - Jude Haris; Nicolas Bohm Agostini; Antonino Tumeo; David R. Kaeli; José Cano 001 (CoRR, 2024)

Designing Efficient LLM Accelerators for Edge Devices. - Jude Haris; Rappy Saha; Wenhao Hu; José Cano 001 (CoRR, 2024)

Accelerating PoT Quantization on Edge Devices. - Rappy Saha; Jude Haris; José Cano 001 (CoRR, 2024)

Accelerating Transposed Convolutions on FPGA-based Edge Devices. - Jude Haris; José Cano 001 (CoRR, 2025)