Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate. - Jue-Hsuan Hsiao; Liang-Gee Chen; Tzi-Dar Chiueh; Chun-Te Chen (ISCAS, 1993)

A hardware-oriented design for weighted median filters. - Chun-Te Chen; Liang-Gee Chen; Jue-Hsuan Hsiao (ASP-DAC, 1995)

High throughput CORDIC-based systolic array design for the discrete cosine transform. - Jue-Hsuan Hsiao; Liang-Gee Chen; Tzi-Dar Chiueh; Chun-Te Chen (IEEE Trans. Circuits Syst. Video Technol., 1995)

A bit-level pipelined VLSI architecture for the running order algorithm. - Chun-Te Chen; Liang-Gee Chen; Jue-Hsuan Hsiao (IEEE Trans. Signal Process., 1997)

Wi-Fi LDPC encoder with approximate lower triangular diverse implementation and verification. - Yi Hua Chen; Jue-Hsuan Hsiao; Zong Yi Siao (SSD, 2014)