A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. - Jens Leenstra; Jürgen Pille; Antje Müller; Wolfram M. Sauer; Rolf Sautter; Dieter F. Wendel (IEEE J. Solid State Circuits, 2001)

The vector fixed point unit of the synergistic processor element of the cell architecture processor. - Nicolas Mäding; Jens Leenstra; Jürgen Pille; Rolf Sautter; Stefan Büttner; Sebastian Ehrenreich; W. Haller (ESSCIRC, 2005)

The circuit design of the synergistic processor element of a CELL processor. - Osamu Takahashi; Russ Cook; Scott R. Cottier; Sang H. Dhong; Brian K. Flachs; Koji Hirairi; Atsushi Kawasumi; Hiroaki Murakami; Hiromi Noro; Hwa-Joon Oh; S. Onish; Juergen Pille; et al. (ICCAD, 2005)

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. - Dac C. Pham; Hans-Werner Anderson; Erwin Behnen; Mark Bolliger; Sanjay Gupta; H. Peter Hofstee; Paul E. Harvey; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; et al. (ASP-DAC, 2006)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. - James D. Warnock; Dieter F. Wendel; Tony Aipperspach; Erwin Behnen; Robert A. Cordes; Sang H. Dhong; Koji Hirairi; Hiroaki Murakami; Shohji Onishi; Dac C. Pham; Jürgen Pille; Stephen D. Posluszny; et al. (IEEE J. Solid State Circuits, 2006)

Implementation of the 65nm Cell Broadband Engine. - Mack W. Riley; Brian K. Flachs; Sang H. Dhong; Gilles Gervais; Steve Weitzel; Michael Wang 001; David Boerstler; Mark Bolliger; John M. Keaty; Jürgen Pille; R. Berry; Osamu Takahashi; et al. (CICC, 2007)

Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V. - Jürgen Pille; Chad Adams; Todd Christensen; Scott R. Cottier; Sebastian Ehrenreich; Fumihiro Kono; Daniel Nelson; Osamu Takahashi; Shunsako Tokito; Otto A. Torreiter; Otto Wagner; Dieter F. Wendel (ISSCC, 2007)

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IBM J. Res. Dev., 2007)

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI. - Osamu Takahashi; Chad Adams; D. Ault; Erwin Behnen; O. Chiang; Scott R. Cottier; Paula K. Coulman; James Culp; Gilles Gervais; M. S. Gray; Y. Itaka; C. J. Johnson; et al. (ISSCC, 2008)

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V. - Juergen Pille; Chad Adams; Todd Christensen; Scott R. Cottier; Sebastian Ehrenreich; Fumihiro Kono; Daniel Nelson; Osamu Takahashi; Shunsako Tokito; Otto A. Torreiter; Otto Wagner; Dieter F. Wendel (IEEE J. Solid State Circuits, 2008)

A 32nm 0.5V-supply dual-read 6T SRAM. - Jente B. Kuang; Jeremy D. Schaub; Fadi H. Gebara; Dieter F. Wendel; Sudesh Saroop; Tuyet Nguyen; Thomas Fröhnel; Antje Müller; Christopher M. Durham; Rolf Sautter; Bryan Lloyd; Bryan J. Robbins; et al. (CICC, 2010)

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. - Jürgen Pille; Dieter F. Wendel; Otto Wagner; Rolf Sautter; Wolfgang Penth; Thomas Fröhnel; Stefan Büttner; Otto A. Torreiter; Martin Eckert; Jose Paredes; David Hrusecky; David Ray; et al. (ISSCC, 2010)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction. - Alexander Fritsch; Michael Kugel; Rolf Sautter; Dieter F. Wendel; Juergen Pille; Otto A. Torreiter; Shankar Kalyanasundaram; Daniel A. Dobson (ESSCIRC, 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology. - Philipp Salz; A. Frisch; Wolfgang Penth; J. Noack; T. Kalla; Rolf Sautter; Michael Kugel; Otto A. Torreiter; G. Sapp; Mike Lee; Eric Fluhr; A. Rozenfeld; et al. (ESSCIRC, 2017)

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. - Christopher J. Gonzalez; Eric Fluhr; Daniel Dreps; David Hogenmiller; Rahul M. Rao; Jose Paredes; Michael S. Floyd; Michael A. Sperling; Ryan Kruse; Vinod Ramadurai; Ryan Nett; Md. Saiful Islam 004; et al. (ISSCC, 2017)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)