The Development of Postech Hand 5. - Juhyoung Lee; Youngil Youm; Wan Kyun Chung (ICRA, 2004)

An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks. - Dongjoo Shin; Jinmook Lee; Jinsu Lee; Juhyoung Lee; Hoi-Jun Yoo (COOL Chips, 2017)

A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices. - Juhyoung Lee; Changhyeon Kim; Sungpill Choi; Dongjoo Shin; Sanghoon Kang; Hoi-Jun Yoo (ISCAS, 2018)

DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture. - Dongjoo Shin; Jinmook Lee; Jinsu Lee; Juhyoung Lee; Hoi-Jun Yoo (IEEE Micro, 2018)

A 15.2 TOPS/W CNN Accelerator with Similar Feature Skipping for Face Recognition in Mobile Devices. - Sangyeob Kim; Juhyoung Lee; Sanghoon Kang; Jinsu Lee; Hoi-Jun Yoo (ISCAS, 2019)

LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16. - Jinsu Lee; Juhyoung Lee; Donghyeon Han; Jinmook Lee; Gwangtae Park; Hoi-Jun Yoo (ISSCC, 2019)

A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices. - Juhyoung Lee; Dongjoo Shin; Jinsu Lee; Jinmook Lee; Sanghoon Kang; Hoi-Jun Yoo (VLSI Circuits, 2019)

A 54.7 fps 3D Point Cloud Semantic Segmentation Processor with Sparse Grouping Based Dilated Graph Convolutional Network for Mobile Devices. - Sangjin Kim; Sangyeob Kim; Juhyoung Lee; Hoi-Jun Yoo (ISCAS, 2020)

7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation. - Sanghoon Kang; Donghyeon Han; Juhyoung Lee; Dongseok Im; Sangyeob Kim; Soyeon Kim; Hoi-Jun Yoo (ISSCC, 2020)

A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping. - Sangyeob Kim; Juhyoung Lee; Sanghoon Kang; Jinmook Lee; Hoi-Jun Yoo (VLSI Circuits, 2020)

Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision. - Ji-Hoon Kim 004; Juhyoung Lee; Jinsu Lee; Hoi-Jun Yoo; Joo-Young Kim 001 (VLSI Circuits, 2020)

SRNPU: An Energy-Efficient CNN-Based Super-Resolution Processor With Tile-Based Selective Super-Resolution in Mobile Devices. - Juhyoung Lee; Jinsu Lee; Hoi-Jun Yoo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices. - Sangyeob Kim; Juhyoung Lee; Sanghoon Kang; Jinsu Lee; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Energy-Efficient Deep Reinforcement Learning Accelerator Designs for Mobile Autonomous Systems. - Juhyoung Lee; Changhyeon Kim; Donghyeon Han; Sangyeob Kim; Sangjin Kim; Hoi-Jun Yoo (AICAS, 2021)

An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-precision Re-training. - Wooyoung Jo; Juhyoung Lee; Seunghyun Park; Hoi-Jun Yoo (A-SSCC, 2021)

An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation. - Donghyeon Han; Dongseok Im; Gwangtae Park; Youngwoo Kim; Seokchan Song; Juhyoung Lee; Hoi-Jun Yoo (COOL CHIPS, 2021)

PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access. - Sangjin Kim; Juhyoung Lee; Dongseok Im; Hoi-Jun Yoo (HCS, 2021)

An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. - Juhyoung Lee; Jihoon Kim 004; Wooyoung Jo; Sangyeob Kim; Sangjin Kim; Donghyeon Han; Jinsu Lee; Hoi-Jun Yoo (HCS, 2021)

OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data. - Juhyoung Lee; Sangyeob Kim; Ji-Hoon Kim 004; Sangjin Kim; Wooyoung Jo; Donghyeon Han; Hoi-Jun Yoo (HCS, 2021)

PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access. - Sangjin Kim; Juhyoung Lee; Dongseok Im; Hoi-Jun Yoo (VLSI Circuits, 2021)

A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. - Juhyoung Lee; Jihoon Kim 004; Wooyoung Jo; Sangyeob Kim; Sangjin Kim; Jinsu Lee; Hoi-Jun Yoo (VLSI Circuits, 2021)

OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer. - Juhyoung Lee; Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Donghyeon Han; Jinsu Lee; Hoi-Jun Yoo (VLSI Circuits, 2021)

GST: Group-Sparse Training for Accelerating Deep Reinforcement Learning. - Juhyoung Lee; Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Hoi-Jun Yoo (CoRR, 2021)

HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching. - Donghyeon Han; Dongseok Im; Gwangtae Park; Youngwoo Kim; Seokchan Song; Juhyoung Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2021)

GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation. - Sanghoon Kang; Donghyeon Han; Juhyoung Lee; Dongseok Im; Sangyeob Kim; Soyeon Kim; Junha Ryu; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2021)

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks. - Ji-Hoon Kim 004; Juhyoung Lee; Jinsu Lee; Jaehoon Heo; Joo-Young Kim 001 (IEEE J. Solid State Circuits, 2021)

A 0.95 mJ/frame DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation. - Donghyeon Han; Dongseok Im; Gwangtae Park; Youngwoo Kim; Seokchan Song; Juhyoung Lee; Hoi-Jun Yoo (AICAS, 2022)

A DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation. - Donghyeon Han; Dongseok Im; Gwangtae Park; Youngwoo Kim; Seokchan Song; Juhyoung Lee; Hoi-Jun Yoo (AICAS, 2022)

Low-power Autonomous Adaptation System with Deep Reinforcement Learning. - Juhyoung Lee; Wooyoung Jo; Seong-Wook Park; Hoi-Jun Yoo (AICAS, 2022)

HNPU-V2: A 46.6 FPS DNN Training Processor for Real-World Environmental Adaptation based Robust Object Detection on Mobile Devices. - Donghyeon Han; Dongseok Im; Gwangtae Park; Youngwoo Kim; Seokchan Song; Juhyoung Lee; Hoi-Jun Yoo (HCS, 2022)

OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer. - Juhyoung Lee; Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Ji-Hoon Kim 004; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2022)

A Mobile DNN Training Processor With Automatic Bit Precision Search and Fine-Grained Sparsity Exploitation. - Donghyeon Han; Dongseok Im; Gwangtae Park; Youngwoo Kim; Seokchan Song; Juhyoung Lee; Hoi-Jun Yoo (IEEE Micro, 2022)

ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor. - Juhyoung Lee; Jihoon Kim 004; Wooyoung Jo; Sangyeob Kim; Sangjin Kim; Hoi-Jun Yoo (IEEE Micro, 2022)

A Low-Power Graph Convolutional Network Processor With Sparse Grouping for 3D Point Cloud Semantic Segmentation in Mobile Devices. - Sangjin Kim; Sangyeob Kim; Juhyoung Lee; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

TSUNAMI: Triple Sparsity-Aware Ultra Energy-Efficient Neural Network Training Accelerator With Multi-Modal Iterative Pruning. - Sangyeob Kim; Juhyoung Lee; Sanghoon Kang; Donghyeon Han; Wooyoung Jo; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Juhyoung Lee; Sangyeob Kim; Donghyeon Han; Hoi-Jun Yoo (ISSCC, 2023)

NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices. - Wooyoung Jo; Sangjin Kim; Juhyoung Lee; Donghyeon Han; Sangyeob Kim; Seungyoon Choi; Hoi-Jun Yoo (VLSI Technology and Circuits, 2023)

SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit. - Sangyeob Kim; Sangjin Kim; Soyeon Um; Soyeon Kim; Juhyoung Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2023)

DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Juhyoung Lee; Sangyeob Kim; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)