A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis. - Kuan-Ju Huang; Wei-Yeh Shih; Jui-Chung Chang; Chih-Wei Feng; Wai-Chi Fang (EMBC, 2013)

A parallel VLSI architecture of singular value decomposition processor for real-time multi-channel EEG system. - Kuan-Ju Huang; Jui-Chung Chang; Chih-Wei Feng; Wai-Chi Fang (ISCE, 2013)

A real-time processing flow for ICA based EEG acquisition system with eye blink artifact elimination. - Kuan-Ju Huang; Jui-Chieh Liao; Wei-Yeh Shih; Chih-Wei Feng; Jui-Chung Chang; Chia-Ching Chou; Wai-Chi Fang (SiPS, 2013)

An efficient VLSI implementation of SVD processor of on-line recursive ICA for real-time EEG system. - Wai-Chi Fang; Jui-Chung Chang; Kuan-Ju Huang; Chih-Wei Feng; Chia-Ching Chou (BioCAS, 2014)

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system. - Wai-Chi Fang; Kuan-Ju Huang; Chia-Ching Chou; Jui-Chung Chang; Gert Cauwenberghs; Tzyy-Ping Jung (EMBC, 2014)

A reliable brain computer interface implemented on an FPGA for a mobile dialing system. - Chih-Wei Feng; Ting-Kuei Hu; Jui-Chung Chang; Wai-Chi Fang (ISCAS, 2014)

A reliable brain computer interface implemented on FPGA for mobile dialing system. - Chih-Wei Feng; Jui-Chung Chang; Wei-Chen Chen; Wai-Chi Fang (ICCE-TW, 2015)

Radiometric Variations of On-Orbit FORMOSAT-5 RSI from Vicarious and Cross-Calibration Measurements. - Tang-Huang Lin; Jui-Chung Chang; Kuo-Hsien Hsu; Yun-Shan Lee; Sheng-Kai Zeng; Gin-Rong Liu; Fuan Tsai; Hai-Po Chan (Remote. Sens., 2019)