A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. - Yen-Huei Chen; Gary Chan; Shao-Yu Chou; Hsien-Yu Pan; Jui-Jen Wu; Robin Lee; Hung-Jen Liao; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2009)

A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications. - Meng-Fan Chang; Jui-Jen Wu; Kuang-Ting Chen; Yung-Chi Chen; Yen-Hui Chen; Robin Lee; Hung-Jen Liao; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2010)

A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme. - Jui-Jen Wu; Yen-Hui Chen; Meng-Fan Chang; Po-Wei Chou; Chien-Yuan Chen; Hung-Jen Liao; Ming-Bin Chen; Yuan-Hua Chu; Wen-Chin Wu; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2011)

A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. - Ming-Pin Chen; Lai-Fu Chen; Meng-Fan Chang; Shu-Meng Yang; Yao-Jen Kuo; Jui-Jen Wu; Mon-Shu Ho; Hsiu-Yun Su; Yuan-Hua Chu; Wen-Chin Wu; Tzu-Yi Yang; Hiroyuki Yamauchi (VLSIC, 2012)

A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances. - Jui-Jen Wu; Meng-Fan Chang; Shau-Wei Lu; Robert Lo; Quincy Li (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. - Meng-Fan Chang; Ming-Bin Chen; Lai-Fu Chen; Shu-Meng Yang; Yao-Jen Kuo; Jui-Jen Wu; Hsiu-Yun Su; Yuan-Hua Chu; Wen-Chin Wu; Tzu-Yi Yang; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Ku-Feng Lin; Yu-Der Chih; Sreedhar Natarajan; Tsung-Yung Jonathan Chang (ISSCC, 2014)

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. - Meng-Fan Chang; Chia-Chen Kuo; Shyh-Shyuan Sheu; Chorng-Jung Lin; Ya-Chin King; Frederick T. Chen; Tzu-Kun Ku; Ming-Jinn Tsai; Jui-Jen Wu; Yu-Der Chih (IEEE J. Solid State Circuits, 2014)

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros. - Meng-Fan Chang; Yu-Fan Lin; Yen-Chen Liu; Jui-Jen Wu; Shin-Jang Shen; Wu-Chin Tsai; Yu-Der Chih (IEEE J. Solid State Circuits, 2015)

Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chrong Jung Lin; Ku-Feng Lin; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2015)

A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. - Tai-Hao Wen; Je-Min Hung; Hung-Hsi Hsu; Yuan Wu 009; Fu-Chun Chang; Chung-Yuan Li; Chih-Han Chien; Chin-I Su; Win-San Khwa; Jui-Jen Wu; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2023)

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices. - Win-San Khwa; Ping-Chun Wu; Jui-Jen Wu; Jian-Wei Su; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; Ren-Shuo Liu; et al. (ISSCC, 2024)

A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. - De-Qi You; Win-San Khwa; Jui-Jen Wu; Chuan-Jia Jhang; Guan-Yi Lin; Po-Jung Chen; Ting-Chien Chiu; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2024)

A 16.42 TOPS/mm2 Reverse Rotating Charge Sharing DRAM Compute-in-Memory Design in 28nm Process. - Tsung-Han Wu; Yu-Tse Shih; Hsin-Yung Fu; Chia Ling Ho; Wai-Chi Fang; Ke-Horng Chen; Kuo-Lin Zheng; Ying-Hsi Lin; Shian-Ru Lin; Tsung-Yen Tsai; Jui-Jen Wu; Meng-Fan Marvin Chang (ISCAS, 2025)

14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices. - Win-San Khwa; Ping-Chun Wu; Jian-Wei Su; Chiao-Yen Cheng; Jun-Ming Hsu; Yu-Chen Chen; Le-Jung Hsieh; Jyun-Cheng Bai; Yu-Sheng Kao; Tsung-Han Lou; Ashwin Sanjay Lele; Jui-Jen Wu; et al. (ISSCC, 2025)

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips. - Ping-Chun Wu; Win-San Khwa; Jui-Jen Wu; Jian-Wei Su; Chuan-Jia Jhang; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; et al. (IEEE J. Solid State Circuits, 2025)