Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. - Wen-Zen Shen; Juinn-Dar Huang; Shih-Min Chao (DAC, 1995)

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (ICCAD, 1995)

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (ICCAD, 1996)

BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. - Jie-Hong R. Jiang; Jing-Yang Jou; Juinn-Dar Huang; Jung-Shian Wei (ASP-DAC, 1997)

Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. - Jie-Hong Roland Jiang; Jing-Yang Jou; Juinn-Dar Huang (DAC, 1998)

On circuit clustering for area/delay tradeoff under capacity and pin constraints. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen; Hsien-Ho Chuang (IEEE Trans. Very Large Scale Integr. Syst., 1998)

ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Unified functional decomposition via encoding for FPGA technology mapping. - Jie-Hong Roland Jiang; Jing-Yang Jou; Juinn-Dar Huang (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Verification on Port Connections. - Geeng-Wei Lee; Juinn-Dar Huang; Jing-Yang Jou; Chun-Yao Wang (ITC, 2004)

Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. - Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (HLDVT, 2005)

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. - Chien-Hua Chen; Geeng-Wei Lee; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2006)

FSM-based transaction-level functional coverage for interface compliance verification. - Man-Yun Su; Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2006)

Fault Dictionary Size Reduction for Million-Gate Large Circuits. - Yu-Ru Hong; Juinn-Dar Huang (ASP-DAC, 2007)

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. - Bu-Ching Lin; Geeng-Wei Lee; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2007)

Low power multiplexer tree design using dynamic propagation path control. - Nan-Shing Li; Juinn-Dar Huang; Han-Jung Huang (APCCAS, 2008)

Cycle-time-aware sequential way-access set-associative cache for low energy consumption. - Chih-Hui Ting; Juinn-Dar Huang; Yu-Hsiang Kao (APCCAS, 2008)

A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. - Wei-Sheng Huang; Yu-Ru Hong; Juinn-Dar Huang; Ya-Shih Huang (ASP-DAC, 2008)

Verification of Pin-Accurate Port Connections. - Geeng-Wei Lee; Juinn-Dar Huang; Chun-Yao Wang; Jing-Yang Jou (IEEE Des. Test Comput., 2008)

CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. - Chia-I Chen; Juinn-Dar Huang (ASP-DAC, 2009)

Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. - Yu-Ju Hong; Ya-Shih Huang; Juinn-Dar Huang (ASP-DAC, 2009)

Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture. - Ya-Shih Huang; Yu-Ju Hong; Juinn-Dar Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Reducing fault dictionary size for million-gate large circuits. - Yu-Ru Hong; Juinn-Dar Huang (ACM Trans. Design Autom. Electr. Syst., 2009)

Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. - Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Expandable MDC-based FFT architecture and its generator for high-performance applications. - Bu-Ching Lin; Yu-Hsiang Wang; Juinn-Dar Huang; Jing-Yang Jou (SoCC, 2010)

A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication. - Chia-I Chen; Juinn-Dar Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

FSM-Based Formal Compliance Verification of Interface Protocols. - Che-Hua Shih; Ya-Ching Yang; Chia-Chih Yen; Juinn-Dar Huang; Jing-Yang Jou (J. Inf. Sci. Eng., 2010)

Throughput optimization for latency-insensitive system with minimal queue insertion. - Juinn-Dar Huang; Yi-Hang Chen; Ya-Chien Ho (ASP-DAC, 2011)

Equivalence checking of scheduling with speculative code transformations in high-level synthesis. - Chi-Hui Lee; Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2011)

Architectural exploration of 3D FPGAs towards a better balance between area and delay. - Chia-I Chen; Bau-Cheng Lee; Juinn-Dar Huang (DATE, 2011)

Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family. - Chia-I Chen; Juinn-Dar Huang (ISVLSI, 2011)

Layer-Aware Design Partitioning for Vertical Interconnect Minimization. - Ya-Shih Huang; Yang-Hsiang Liu; Juinn-Dar Huang (ISVLSI, 2011)

Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. - Juinn-Dar Huang; Chia-I Chen; Yen-Ting Lin; Wan-Ling Hsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only). - Juinn-Dar Huang; Ya-Shih Huang; Mi-Yu Hsu; Han-Yuan Chang (FPGA, 2012)

Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees. - Juinn-Dar Huang; Chia-Hung Liu; Ting-Wei Chiang (ICCAD, 2012)

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. - Juinn-Dar Huang; Chia-I Chen; Wan-Ling Hsu; Yen-Ting Lin; Jing-Yang Jou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing. - Chia-Hung Liu; Hao-Han Chang; Tung-Che Liang; Juinn-Dar Huang (ICCAD, 2013)

Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration. - Tsung-Yi Ho; Juinn-Dar Huang; Paul Pop (SoCC, 2013)

Latency-optimization synthesis with module selection for digital microfluidic biochips. - Chia-Hung Liu; Kuang-Cheng Liu; Juinn-Dar Huang (SoCC, 2013)

Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips. - Ting-Wei Chiang; Chia-Hung Liu; Juinn-Dar Huang (VLSI-DAT, 2013)

Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips. - Juinn-Dar Huang; Chia-Hung Liu; Huei-Shan Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Sample preparation for droplet-based microfluidics. - Juinn-Dar Huang; Chia-Hung Liu (ISIC, 2014)

Two-staged parallel layer-aware partitioning for 3D designs. - Yi-Hang Chen; Yi-Ting Chen; Juinn-Dar Huang (VLSI-DAT, 2014)

ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication. - Bu-Ching Lin; Juinn-Dar Huang; Jing-Yang Jou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors. - Bu-Ching Lin; Ming-En Shih; Juinn-Dar Huang; Jing-Yang Jou (J. Inf. Sci. Eng., 2014)

Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers. - Chi-Mei Huang; Chia-Hung Liu; Juinn-Dar Huang (DATE, 2015)

ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays. - Yi-Hang Chen; Yang Chen; Juinn-Dar Huang (VLSI-DAT, 2015)

TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance. - Ya-Shih Huang; Han-Yuan Chang; Juinn-Dar Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips. - Chia-Hung Liu; Ting-Wei Chiang; Juinn-Dar Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models. - Chia-Hung Liu; Kuo-Cheng Shen; Juinn-Dar Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Chain-based pin count minimization for general-purpose digital microfluidic biochips. - Yung-Chun Lei; Chen-Shing Hsu; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2016)

Reactant cost minimization through target concentration selection on microfluidic biochips. - Yung-Chun Lei; Yi-Ling Chen 005; Juinn-Dar Huang (BioCAS, 2016)

Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing models. - Yung-Chun Lei; Tung-Hsuan Lin; Juinn-Dar Huang (SoCC, 2016)

Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints. - Yi-Hang Chen; Jian-Yu Chen; Juinn-Dar Huang (ACM J. Emerg. Technol. Comput. Syst., 2016)

Defect-aware synthesis for reconfigurable single-electron transistor arrays. - Juinn-Dar Huang; Yi-Hang Chen; Jia-Shin Lu (VLSI-SoC, 2017)

Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips. - Sukanta Bhattacharjee; Sudip Poddar; Sudip Roy 001; Juinn-Dar Huang; Bhargab B. Bhattacharya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip. - Sukanta Bhattacharjee; Robert Wille; Juinn-Dar Huang; Bhargab B. Bhattacharya (DATE, 2018)

Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips. - Yung-Chun Lei; Tien-Kuo Lin; Juinn-Dar Huang (ISVLSI, 2018)

Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. - Chia-Cheng Wu; Kung-Han Ho; Juinn-Dar Huang; Chun-Yao Wang (ISVLSI, 2018)

A Comprehensive Security System for Digital Microfluidic Biochips. - Chun-Yu Lin; Juinn-Dar Huang; Hailong Yao; Tsung-Yi Ho (ITC-Asia, 2018)

Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips. - Juinn-Dar Huang; Chia-Hung Liu; Wei-Hao Yang (VLSI-SoC, 2018)

Concentration-Resilient Mixture Preparation with Digital Microfluidic Lab-on-Chip. - Sukanta Bhattacharjee; Yi-Ling Chen 005; Juinn-Dar Huang; Bhargab B. Bhattacharya (ACM Trans. Embed. Comput. Syst., 2018)

Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs. - Ling-Yen Song; Yi-Ling Chen 005; Yung-Chun Lei; Juinn-Dar Huang (ICCD, 2019)

Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips. - Ling-Yen Song; Yu-Ying Li; Yung-Chun Lei; Juinn-Dar Huang (ISVLSI, 2019)

Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models. - Kang-Yi Fan; Shigeru Yamashita; Juinn-Dar Huang (VLSI-DAT, 2019)

Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips. - Ankur Gupta 002; Juinn-Dar Huang; Shigeru Yamashita; Sudip Roy 001 (ACM Trans. Design Autom. Electr. Syst., 2019)

A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization. - Yi Lu; Yi-Lin Wu; Juinn-Dar Huang (AICAS, 2020)

High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme. - Yi-Lin Wu; Yi Lu; Juinn-Dar Huang (ISCAS, 2020)

Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip. - Sukanta Bhattacharjee; Robert Wille; Juinn-Dar Huang; Bhargab B. Bhattacharya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing. - Wei-Chen Lin; Ya-Chu Chang; Juinn-Dar Huang (AICAS, 2021)

Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip. - Shuaijie Ying; Sudip Roy 001; Juinn-Dar Huang; Shigeru Yamashita (DSD, 2021)

Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips. - Ling-Yen Song; Chih-Shen Yeh; Chien-Nan Liu; Juinn-Dar Huang (VLSI-DAT, 2021)

All-You-Can-Fit 8-Bit Flexible Floating-Point Format for Accurate and Memory-Efficient Inference of Deep Neural Networks. - Cheng-Wei Huang; Tim-Wei Chen; Juinn-Dar Huang (CoRR, 2021)

Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. - Chia-Cheng Wu; Yi-Hsiang Hu; Chia-Chun Lin; Yung-Chih Chen; Juinn-Dar Huang; Chun-Yao Wang (ACM J. Emerg. Technol. Comput. Syst., 2021)

An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability. - Chia-Heng Hu; I-Hao Tseng; Pei-Hsuan Kuo; Juinn-Dar Huang (AICAS, 2022)

Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. - Ling-Yen Song; Tung-Chieh Kuo; Ming-Hung Wang; Chien-Nan Jimmy Liu; Juinn-Dar Huang (ASP-DAC, 2022)

Capture the Devil in the Details via Partition-then-Ensemble on Higher Resolution Images. - Yung-Han Chen; Yi-Jen Ju; Juinn-Dar Huang (DFUC@MICCAI, 2022)

Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets. - Wei-Cheng Chou; Cheng-Wei Huang; Juinn-Dar Huang (VLSI-DAT, 2022)

Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. - Kang-Yi Fan; Jyun-Hua Chen; Chien-Nan Liu; Juinn-Dar Huang (VLSI-DAT, 2022)

Hardware-Friendly Activation Function Designs and Its Efficient VLSI Implementations for Transformer-Based Applications. - Yu-Hsiang Huang; Pei-Hsuan Kuo; Juinn-Dar Huang (AICAS, 2023)

Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning. - Pei-Hsuan Kuo; Yu-Hsiang Huang; Juinn-Dar Huang (AICAS, 2023)

An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis. - Shan-Hui Chou; Ting-Yun Hsiao; Jing-Yang Jou; Juinn-Dar Huang (VLSI-SoC, 2023)

Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. - Ling-Yen Song; Chih-Yun Chou; Tung-Chieh Kuo; Chien-Nan Liu; Juinn-Dar Huang (ACM Trans. Design Autom. Electr. Syst., 2023)

A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems. - Yu-Da Chu; Pei-Hsuan Kuo; Lyu-Ming Ho; Juinn-Dar Huang (AICAS, 2024)

NYCU-NLP at EXIST 2024: Leveraging Transformers with Diverse Annotations for Sexism Identification in Social Networks. - Yi-Zeng Fang; Lung-Hao Lee; Juinn-Dar Huang (CLEF (Working Notes), 2024)

Enhancing Brain Tumor Segmentation with Deep Supervision and Attention Mechanisms: Advances in the nnU-Net Framework. - Yi-Zeng Fang; Juinn-Dar Huang (ISBI, 2024)

A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications. - Meng-Hsun Hsieh; Xuan-Hong Li; Yu-Hsiang Huang; Pei-Hsuan Kuo; Juinn-Dar Huang (ISCAS, 2024)

SMILE-UHURA Challenge - Small Vessel Segmentation at Mesoscopic Scale from Ultra-High Resolution 7T Magnetic Resonance Angiograms. - Soumick Chatterjee; Hendrik Mattern; Marc Dörner; Alessandro Sciarra; Florian Dubost; Hannes Schnurre; Rupali Khatun; Chun-Chih Yu; Tsung-Lin Hsieh; Yi-Shan Tsai; Yi-Zeng Fang; Yung-Ching Yang; et al. (CoRR, 2024)

Diabetic foot ulcers segmentation challenge report: Benchmark and analysis. - Moi Hoon Yap; Bill Cassidy; Michal Byra; Ting-Yu Liao; Huahui Yi; Adrian Galdran; Yung-Han Chen; Raphael Brüngel; Sven Koitka; Christoph M. Friedrich; Yu-Wen Lo; Ching-Hui Yang; et al. (Medical Image Anal., 2024)

An Accurate and Compact Design Integrating Seven Common Nonlinear Functions in Deep Learning. - Jye-En Wu; Ting-Wei Hu; Chih-Yao Liang; Juinn-Dar Huang (ISCAS, 2025)

Anomaly Detection for Hybrid Butterfly Subspecies via Probability Filtering. - Bo-Kai Ruan; Yi-Zeng Fang; Hong-Han Shuai; Juinn-Dar Huang (CoRR, 2025)