A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. - Markus Hiienkari; Jukka Teittinen; Lauri Koskinen; Matthew J. Turnquist; Mikko Kaltiokallio (CICC, 2014)

Towards Hardware-driven Design of Low-energy Algorithms for Data Analysis. - Indre Zliobaite; Jaakko Hollmén; Lauri Koskinen; Jukka Teittinen (SIGMOD Rec., 2014)

A Performance Case-Study on Memristive Computing-in-Memory Versus Von Neumann Architecture. - Lauri Koskinen; Jari Tissari; Jukka Teittinen; Eero Lehtonen; Mika Laiho; Jussi H. Poikonen (DCC, 2016)

A 5.3 pJ/op approximate TTA VLIW tailored for machine learning. - Jukka Teittinen; Markus Hiienkari; Indre Zliobaite; Jaakko Hollmén; Heikki Berg; Juha Heiskala; Timo Viitanen; Jesse Simonsson; Lauri Koskinen (Microelectron. J., 2017)

A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan. - Markus Hiienkari; Navneet Gupta; Jukka Teittinen; Jesse Simonsson; Matthew J. Turnquist; Jonas Eriksson; Risto Anttila; Ohto Myllynen; Hannu Rämäkkö; Sofia Mäkikyrö; Lauri Koskinen (COOL CHIPS, 2020)