Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis. - Dominique Borrione; Julia Dushina; Laurence Pierre (SBCCI, 1998)

Vérification formelle des résultats de la synthèse de haut niveau. (Formal verification of high level synthesis results). - Julia Dushina (1999)

A compositional model for the functional verification of high-level synthesis results. - Dominique Borrione; Julia Dushina; Laurence V. Pierre (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Semi-Formal Test Generation with Genevieve. - Julia Dushina; Mike Benjamin; Daniel Geist (DAC, 2001)

Semi-Formal Test Generation for a Block of Industrial DSP. - Julia Dushina; Mike Benjamin; Daniel Geist (VTS, 2001)

Semi-formal test generation and resolving a temporal abstraction problem in practice: industrial application. - Julia Dushina; Mike Benjamin; Daniel Geist (ASP-DAC, 2003)