SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. - Julian J. H. Pontes; Rafael Soares; Ewerson Carvalho; Fernando Moraes 001; Ney Calazans (ICCD, 2007)

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. - Julian J. H. Pontes; Matheus T. Moreira; Rafael Soares; Ney Laert Vilar Calazans (ISVLSI, 2008)

Hermes-A - An Asynchronous NoC Router with Distributed Routing. - Julian J. H. Pontes; Matheus T. Moreira; Fernando Moraes 001; Ney Calazans (PATMOS, 2010)

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. - Julian J. H. Pontes; Matheus T. Moreira; Fernando Moraes 001; Ney Calazans (SoCC, 2010)

Adapting a C-element design flow for low power. - Matheus T. Moreira; Bruno Cruz de Oliveira; Julian J. H. Pontes; Fernando Moraes 001; Ney Calazans (ICECS, 2011)

A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. - Matheus T. Moreira; Bruno Cruz de Oliveira; Julian J. H. Pontes; Ney Calazans (SoCC, 2011)

Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. - Julian J. H. Pontes; Ney Calazans; Pascal Vivet (ASYNC, 2012)

An accurate Single Event Effect digital design flow for reliable system level design. - Julian J. H. Pontes; Ney Calazans; Pascal Vivet (DATE, 2012)

Soft error mitigation in asynchronous networks on chip. - Julian J. H. Pontes (2012)

Parity check for m-of-n delay insensitive codes. - Julian J. H. Pontes; Ney Calazans; Pascal Vivet (IOLTS, 2013)

H2A: A hardened asynchronous network on chip. - Julian J. H. Pontes; Ney Calazans; Pascal Vivet (SBCCI, 2013)

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. - Matheus T. Moreira; Julian J. H. Pontes; Ney Laert Vilar Calazans (ISQED, 2014)

Two-phase protocol converters for 3D asynchronous 1-of-n data links. - Julian J. H. Pontes; Pascal Vivet; Yvain Thonnart (ASP-DAC, 2015)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)