Hardware/software co-compilation with the Nymble system. - Jens Huthmann; Björn Liebig; Julian Oppermann; Andreas Koch 001 (ReCoSoC, 2013)

Automatic high-level synthesis of multi-threaded hardware accelerators. - Jens Huthmann; Julian Oppermann; Andreas Koch 001 (FPL, 2014)

Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators. - Julian Oppermann; Andreas Koch 001; Ting Yu 012; Oliver Sinnen (FPL, 2015)

ILP-based modulo scheduling for high-level synthesis. - Julian Oppermann; Andreas Koch 001; Melanie Reuter-Oppermann; Oliver Sinnen (CASES, 2016)

Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis. - Julian Oppermann; Andreas Koch 001 (UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld, 2016)

Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models. - Ting Yu 012; Julian Oppermann; Chris P. Bradley; Oliver Sinnen (Concurr. Comput. Pract. Exp., 2016)

Synthesis of interleaved multithreaded accelerators from OpenMP loops. - Lukas Sommer; Julian Oppermann; Jaco A. Hofmann; Andreas Koch 001 (ReConFig, 2017)

Improved High-Level Synthesis for Complex CellML Models. - Björn Liebig; Julian Oppermann; Oliver Sinnen; Andreas Koch 001 (ARC, 2018)

GeMS: a generator for modulo scheduling problems: work in progress. - Julian Oppermann; Sebastian Vollbrecht; Melanie Reuter-Oppermann; Oliver Sinnen; Andreas Koch 001 (CASES, 2018)

NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management. - Tobias Vinçon; Sergej Hardock; Christian Riegger; Julian Oppermann; Andreas Koch 001; Ilia Petrov 001 (EDBT, 2018)

Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis. - Julian Oppermann; Melanie Reuter-Oppermann; Lukas Sommer; Oliver Sinnen; Andreas Koch 001 (FPL, 2018)

ILP-Based Modulo Scheduling and Binding for Register Minimization. - Patrick Sittel; Martin Kumm; Julian Oppermann; Konrad Möller; Peter Zipf; Andreas Koch 001 (FPL, 2018)

Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. - Lukas Sommer; Julian Oppermann; Alejandro Molina 001; Carsten Binnig; Kristian Kersting; Andreas Koch 001 (ICCD, 2018)

Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language. - Robin Kruppe; Julian Oppermann; Lukas Sommer; Andreas Koch 001 (CGO, 2019)

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. - Julian Oppermann; Patrick Sittel; Martin Kumm; Melanie Reuter-Oppermann; Andreas Koch 001; Oliver Sinnen (Euro-Par, 2019)

SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. - Julian Oppermann; Lukas Sommer; Lukas Weber; Melanie Reuter-Oppermann; Andreas Koch 001; Oliver Sinnen (FPT, 2019)

Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. - Lukas Weber; Lukas Sommer; Julian Oppermann; Alejandro Molina 001; Kristian Kersting; Andreas Koch 001 (FPT, 2019)

SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. - Julian Oppermann; Lukas Sommer; Andreas Koch 001 (J. Supercomput., 2019)

Exact and Practical Modulo Scheduling for High-Level Synthesis. - Julian Oppermann; Melanie Reuter-Oppermann; Lukas Sommer; Andreas Koch 001; Oliver Sinnen (ACM Trans. Reconfigurable Technol. Syst., 2019)

Advances in ILP-based Modulo Scheduling for High-Level Synthesis. - Julian Oppermann (2019)

Active Storage. - Ilia Petrov 001; Tobias Vinçon; Andreas Koch 001; Julian Oppermann; Sergey Hardock; Christian Riegger (Encyclopedia of Big Data Technologies, 2019)

Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs. - Hanna Kruppe; Lukas Sommer; Lukas Weber; Julian Oppermann; Cristian Axenie; Andreas Koch 001 (SAMOS, 2021)

SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors. - Mihaela Damian; Julian Oppermann; Christoph Spang 001; Andreas Koch 001 (DAC, 2022)

The Scale4Edge RISC-V Ecosystem. - Wolfgang Ecker; Peer Adelt; Wolfgang Müller 003; Reinhold Heckmann; Milos Krstic; Vladimir Herdt; Rolf Drechsler; Gerhard Angst; Ralf Wimmer 001; Andreas Mauderer; Rafael Stahl; Karsten Emrich; et al. (DATE, 2022)

Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs. - Christoph Weckert; Leonardo Solis-Vasquez; Julian Oppermann; Andreas Koch 001; Oliver Sinnen (SC Workshops, 2023)

Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language. - Julian Oppermann; Brindusa Mihaela Damian-Kosterhon; Florian Meisel; Tammo Mürmann; Eyck Jentzsch; Andreas Koch 001 (ASPLOS (3), 2024)

Experiences Building an MLIR-Based SYCL Compiler. - Ettore Tiotto; Victor Perez 001; Whitney Tsang; Lukas Sommer; Julian Oppermann; Victor Lomüller; Mehdi Goli 001; James Brodman (CGO, 2024)

Runtime Instantiation of Kernels for Fast Fourier Transforms Using SYCL Specialization Constants. - Victor Perez 001; Victor Lomüller; Lukas Sommer; Julian Oppermann; Romain Biessy; Tadej Ciglaric; Mehdi Goli 001 (Euro-Par Workshops (1), 2024)

On Demand Specialization of SYCL Kernels with Specialization Constant Length Allocations (SCLA). - Victor Perez 001; Victor Lomüller; Lukas Sommer; Julian Oppermann; Romain Biessy; Tadej Ciglaric; Mehdi Goli 001 (IWOCL, 2024)