Human++: autonomous wireless sensors for body area networks. - Bert Gyselinckx; Chris Van Hoof; Julien Ryckaert; Refet Firat Yazicioglu; Paolo Fiorini; Vladimir Leonov (CICC, 2005)

Ultra wide-band body area channel model. - Andrew Fort; Claude Desset; Julien Ryckaert; Philippe De Doncker; Leo Van Biesen; Stéphane Donnay (ICC, 2005)

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. - Julien Ryckaert; Claude Desset; Andrew Fort; Mustafa Badaroglu; Vincent De Heyn; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Bart van Poucke; Bert Gyselinckx (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. - Julien Ryckaert; Mustafa Badaroglu; Vincent De Heyn; Geert Van der Plas; Pierluigi Nuzzo 001; Andrea Baschirotto; Stefano D'Amico; Claude Desset; Hans Suys; Michael Libois; Bart van Poucke; Piet Wambacq; et al. (ISSCC, 2006)

Human++: Emerging Technology for Body Area Networks. - Bert Gyselinckx; Ruud J. M. Vullers; Chris Van Hoof; Julien Ryckaert; Refet Firat Yazicioglu; Paolo Fiorini; Vladimir Leonov (VLSI-SoC, 2006)

Human++: Emerging Technology for Body Area Networks. - Julien Penders; Bert Gyselinckx; Ruud J. M. Vullers; Olivier Rousseaux; Mladen Berekovic; Michael De Nil; Chris Van Hoof; Julien Ryckaert; Refet Firat Yazicioglu; Paolo Fiorini; Vladimir Leonov (VLSI-SoC (Selected Papers), 2006)

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. - Mustafa Badaroglu; Claude Desset; Julien Ryckaert; Vincent De Heyn; Geert Van der Plas; Piet Wambacq; Bart van Poucke (EURASIP J. Wirel. Commun. Netw., 2006)

Ultra-wideband channel model for communication around the human body. - Andrew Fort; Julien Ryckaert; Claude Desset; Philippe De Doncker; Piet Wambacq; Leo Van Biesen (IEEE J. Sel. Areas Commun., 2006)

A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. - Vincent De Heyn; Geert Van der Plas; Julien Ryckaert; Jan Craninckx (ESSCIRC, 2007)

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. - Julien Ryckaert; Geert Van der Plas; Vincent De Heyn; Claude Desset; Geert Vanwijnsberghe; Bart van Poucke; Jan Craninckx (ISSCC, 2007)

Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. - Claude Desset; Mustafa Badaroglu; Julien Ryckaert; Bart van Poucke (VTC Spring, 2007)

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. - Julien Ryckaert; Geert Van der Plas; Vincent De Heyn; Claude Desset; Bart van Poucke; Jan Craninckx (IEEE J. Solid State Circuits, 2007)

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. - Julien Ryckaert; Marian Verhelst; Mustafa Badaroglu; Stefano D'Amico; Vincent De Heyn; Claude Desset; Pierluigi Nuzzo 001; Bart van Poucke; Piet Wambacq; Andrea Baschirotto; Wim Dehaene; Geert Van der Plas (IEEE J. Solid State Circuits, 2007)

A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. - Jonathan Borremans; Julien Ryckaert; Piet Wambacq; Maarten Kuijk; Jan Craninckx (ESSCIRC, 2008)

A Low Power, Reconfigurable IR-UWB System. - Marian Verhelst; Julien Ryckaert; Yves Vanderperren; Wim Dehaene (ICC, 2008)

A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. - Lynn Bos; Gerd Vandersteen; Julien Ryckaert; Pieter Rombouts; Yves Rolain; Geert Van der Plas (ISSCC, 2009)

A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS. - Vito Giannini; Pierluigi Nuzzo 001; Charlotte Soens; Kameswaran Vengattaramane; Michiel Steyaert; Julien Ryckaert; Michaël Goffioul; Björn Debaillie; Joris Van Driessche; Jan Craninckx; Mark Ingels (ISSCC, 2009)

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. - Jonathan Borremans; Julien Ryckaert; Claude Desset; Maarten Kuijk; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2009)

A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS. - Vito Giannini; Pierluigi Nuzzo 001; Charlotte Soens; Kameswaran Vengattaramane; Julien Ryckaert; Michaël Goffioul; Björn Debaillie; Jonathan Borremans; Joris Van Driessche; Jan Craninckx; Mark Ingels (IEEE J. Solid State Circuits, 2009)

A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. - Julien Ryckaert; Jonathan Borremans; Bob Verbruggen; Lynn Bos; Costantino Armiento; Jan Craninckx; Geert Van der Plas (IEEE J. Solid State Circuits, 2009)

An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation. - Arnd Geis; Pierluigi Nuzzo; Julien Ryckaert; Yves Rolain; Gerd Vandersteen; Jan Craninckx (DATE, 2010)

A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS. - Alonso Morgado; Rocío del Río; José M. de la Rosa 001; Lynn Bos; Julien Ryckaert; Geert Van der Plas (ESSCIRC, 2010)

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. - Lynn Bos; Gerd Vandersteen; Pieter Rombouts; Arnd Geis; Alonso Morgado; Yves Rolain; Geert Van der Plas; Julien Ryckaert (IEEE J. Solid State Circuits, 2010)

A 0.5 mm 2 Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler. - Arnd Geis; Julien Ryckaert; Lynn Bos; Gerd Vandersteen; Yves Rolain; Jan Craninckx (IEEE J. Solid State Circuits, 2010)

DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow. - Dragomir Milojevic; Herman Oprins; Julien Ryckaert; Paul Marchal; Geert Van der Plas (CICC, 2011)

A calibrated pathfinding model for signal integrity analysis on interposer. - Jaemin Kim; Sunyoung Kim; Julien Ryckaert; Mikael Detalle; Nele Van Hoovels; Pol Marchal (CICC, 2012)

Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator. - Michal Rakowski; Julien Ryckaert; Marianna Pantouvaki; Hui Yu; Wim Bogaerts; Kristin De Meyer; Michiel Steyaert; Philippe P. Absil; Joris Van Campenhout (CICC, 2012)

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. - Ewout Martens; André Bourdoux; Aïssa Couvreur; Robert Fasthuber; Peter Van Wesemael; Geert Van der Plas; Jan Craninckx; Julien Ryckaert (IEEE J. Solid State Circuits, 2012)

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. - Arindam Mallik; Paul Zuber; Tsung-Te Liu; Bharani Chava; Bhavana Ballal; Pablo Royer Del Bario; Rogier Baert; Kris Croes; Julien Ryckaert; Mustafa Badaroglu; Abdelkarim Mercha; Diederik Verkest (DAC, 2013)

Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter. - Michal Rakowski; Marianna Pantouvaki; Hui Yu; Wim Bogaerts; Kristin De Meyer; Michiel Steyaert; Bradley Snyder; Peter O'Brien; Julien Ryckaert; Philippe Absil; Joris Van Campenhout (OFC/NFOEC, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy. - Santhosh Kumar Rethinagiri; Oscar Palomar; Anita Sobe; Thomas Knauth; Wojciech M. Barczynski; Gulay Yalcin; Yarco Hayduk; Adrián Cristal; Osman S. Unsal; Pascal Felber; Christof Fetzer; Julien Ryckaert; et al. (DSD, 2014)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Impact of interconnect multiple-patterning variability on SRAMs. - Ioannis Karageorgos; Michele Stucchi; Praveen Raghavan; Julien Ryckaert; Zsolt Tokei; Diederik Verkest; Rogier Baert; Sushil Sakhare; Wim Dehaene (DATE, 2015)

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (ICICDT, 2015)

Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue. - Julien Ryckaert (ISPD, 2016)

SRAM designs for 5nm node and beyond: Opportunities and challenges. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Alessio Spessot; Diederik Verkest; Anda Mocuta (ICICDT, 2017)

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. - Trong Huynh Bao; Julien Ryckaert; Zsolt Tokei; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. - Trong Huynh Bao; Anabela Veloso; Sushil Sakhare; Philippe Matagne; Julien Ryckaert; Manu Perumkunnil; Davide Crotti; Farrukh Yasin; Alessio Spessot; Arnaud Furnémont; Gouri Sankar Kar; Anda Mocuta (DAC, 2019)

Device Scaling roadmap and its implications for Logic and Analog platform. - Alessio Spessot; Bertrand Parvais; Amita Rawat; Kenichi Miyaguchi; Pieter Weckx; Doyoung Jang; Julien Ryckaert (BCICTS, 2020)

Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. - Edouard Giacomin; Jürgen Bömmels; Julien Ryckaert; Francky Catthoor; Pierre-Emmanuel Gaillardon (VLSI-SOC, 2020)

3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. - Edouard Giacomin; Jürgen Bömmels; Julien Ryckaert; Francky Catthoor; Pierre-Emmanuel Gaillardon (VLSI-SoC (Selected Papers), 2020)

Heterogeneous 3D Integration for a RISC-V System With STT-MRAM. - Lingjun Zhu; Lennart Bamberg; Anthony Agnesina; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Julien Ryckaert; Alberto García-Ortiz; Sung Kyu Lim (IEEE Comput. Archit. Lett., 2020)

Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. - Amita Rawat; Krishna K. Bhuwalka; Philippe Matagne; Bjorn Vermeersch; Hao Wu; Geert Hellings; Julien Ryckaert; Changze Liu (ESSDERC, 2021)

Design enablement of CFET devices for sub-2nm CMOS nodes. - Odysseas Zografos; Bilal Chehab; Pieter Schuddinck; Gioele Mirabelli; Naveen Kakarla; Yang Xiang; Pieter Weckx; Julien Ryckaert (DATE, 2022)

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. - Rongmei Chen; Giuliano Sisto; Michele Stucchi; Anne Jourdain; Kenichi Miyaguchi; Pieter Schuddinck; P. Woeltgens; H. Lin; Naveen Kakarla; Anabela Veloso; Dragomir Milojevic; Odysseas Zografos; et al. (VLSI Technology and Circuits, 2022)

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. - Pieter Schuddinck; Fabian M. Bufler; Yang Xiang; Anita Farokhnejad; Gioele Mirabelli; Anne Vandooren; Bilal Chehab; A. Gupta; César Roda Neve; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2022)

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. - Kateryna Serbulova; S.-H. Chen; Geert Hellings; Anabela Veloso; Anne Jourdain; Dimitri Linten; Jo De Boeck; Guido Groeseneken; Julien Ryckaert; Geert Van der Plas; Eric Beyne; Eugenio Dentoni Litta; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters. - Bjorn Vermeersch; Erik Bury; Yang Xiang; Pieter Schuddinck; Krishna K. Bhuwalka; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2022)

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. - Giuliano Sisto; Odysseas Zografos; Bilal Chehab; Naveen Kakarla; Yang Xiang; Dragomir Milojevic; Pieter Weckx; Geert Hellings; Julien Ryckaert (IEEE Trans. Very Large Scale Integr. Syst., 2022)

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. - Carlos Escuin; Fernando García-Redondo; Mahdi Zahedi; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; José María Llabería; James Myers; Julien Ryckaert; Dwaipayan Biswas; Francky Catthoor (ICECS, 2023)

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). - Subrat Mishra; Sankatali Venkateswarlu; Bjorn Vermeersch; Moritz Brunion; Melina Lofrano; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; Gaspard Hiblot; Geert Van der Plas; Pieter Weckx; et al. (IRPS, 2023)

Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications. - Mohit Kumar Gupta 001; Manu Perumkunnil; Dwaipayan Biswas; Saeideh Alinezhad Chamazcoti; Gouri Sankar Kar; Arnaud Furnémont; Julien Ryckaert (ISCAS, 2023)

Impact of interconnects enhancement on SRAM design beyond 5nm technology node. - Mohit Kumar Gupta 001; Pieter Weckx; Manu Perumkunnil Komalan; Julien Ryckaert (ISCAS, 2023)

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. - Giuliano Sisto; R. Preston; Rongmei Chen; Gioele Mirabelli; Anita Farokhnejad; Yun Zhou; Ivan Ciofi; Anne Jourdain; A. Veloso; Michele Stucchi; Odysseas Zografos; Pieter Weckx; et al. (VLSI Technology and Circuits, 2023)

PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. - S. Yang; Pieter Schuddinck; Marie Garcia Bardon; Yang Xiang; Anabela Veloso; B. T. Chan; Gioele Mirabelli; Gaspard Hiblot; Geert Hellings; Julien Ryckaert (VLSI Technology and Circuits, 2023)

3D SRAM Macro Design in 3D Nanofabric Process Technology. - Dawit Burusie Abdi; Shairfe Muhammad Salahuddin; Jürgen Bömmels; Edouard Giacomin; Pieter Weckx; Julien Ryckaert; Geert Hellings; Francky Catthoor (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. - Nesara Eranna Bethur; Pruek Vanna-Iampikul; Odysseas Zografos; Lingjun Zhu; Giuliano Sisto; Dragomir Milojevic; Alberto García Ortiz; Geert Hellings; Julien Ryckaert; Francky Catthoor; Sung Kyu Lim (DAC, 2024)

Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers. - Michael T. Niemier; Zephan M. Enciso; M. Sharifi; Xiaobo Sharon Hu; Ian O'Connor; A. Graening; R. Sharma; P. Gupta; Jerónimo Castrillón; João Paulo C. de Lima; Asif Ali Khan; Hamid Farzaneh; et al. (DATE, 2024)

Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies. - Nitish Kumar; Sankatali Venkateswarlu; Yukai Chen; Moritz Brunion; Subrat Mishra; Ankur Gupta; Pushpapraj Singh; Francky Catthoor; James Myers; Julien Ryckaert; Dwaipayan Biswas (IRPS, 2024)

Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. - Subrat Mishra; Bjorn Vermeersch; Sankatali Venkateswarlu; Halil Kukner; A. Sharma; G. Mirabeli; Fabian M. Bufler; Moritz Brunion; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; et al. (IRPS, 2024)

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. - Sudipta Das; Samuel Riedel; Marco Bertuletti; Luca Benini; Moritz Brunion; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (ISCAS, 2024)

STCO: Driving the More than Moore Era. - Dwaipayan Biswas; James Myers; Srikanth B. Samavedam; Julien Ryckaert (ISVLSI, 2024)

Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet. - Yukai Chen; Sankatali Venkateswarlu; Subrat Mishra; Julien Ryckaert; James Myers; Dwaipayan Biswas (ISVLSI, 2024)

Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems. - Aakash Patel; Dwaipayan Biswas; Joyjit Kundu; Yoojin Ban; Nicolas Pantano; Arindam Mallik; Julien Ryckaert; James Myers (ISVLSI, 2024)

On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies. - Siva Satyendra Sahoo; Dawit Burusie Abdi; Julien Ryckaert; James Myers; Dwaipayan Biswas (SOCC, 2024)

Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). - S. Mishra; Bjorn Vermeersch; Sankatali Venkateswarlu; Halil Kukner; Gioele Mirabelli; Fabian M. Bufler; Moritz Brunion; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; Francky Catthoor; et al. (VLSI Technology and Circuits, 2024)

Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. - Yun Zhou; S. C. Song; Halil Kükner; Giuliano Sisto; Sheng Yang; Anita Farokhnejad; Mohamed Naeim; Moritz Brunion; Ji-Yung Lin; Odysseas Zografos; Pieter Weckx; Shashank Ekbote; et al. (VLSI Technology and Circuits, 2024)

Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures. - Leandro Mateus Giacomini Rocha; Refik Bilgic; Mohamed Naeim; Sudipta Das; Herman Oprins; Amirreza Yousefzadeh; Mario Konijnenburg; Dragomir Milojevic; James Myers; Julien Ryckaert; Dwaipayan Biswas (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. - Hsiao-Hsuan Liu; Carlo Gilardi; Shairfe Muhammad Salahuddin; Zhenlin Pei; Pieter Schuddinck; Yang Xiang; Pieter Weckx; Geert Hellings; Marie Garcia Bardon; Julien Ryckaert; Chenyun Pan; Subhasish Mitra; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Late Breaking Results: Thermal Feasibility of Backside Integrated LDOs in 2.5D/3D System-in-Package Using Nanosheet Technology. - Yukai Chen; Subrat Mishra; Julien Ryckaert; Dwaipayan Biswas; James Myers (DATE, 2025)

Design Technology Co-Optimization of 3D SRAM Macro in Nanosheet Technology for High-Bandwidth Applications. - Anurag Swarnkar; Dawit Burusie Abdi; Bhawana Kumari; Priya Venugopal; Nicolas Pantano; Geert Hellings; Jaydeep Kulkarni; Dwaipayan Biswas; Julien Ryckaert; Fernando García-Redondo (IMW, 2025)

Framework for Augmenting Main Memory with CXL-connected Emerging Memory Alternatives. - Khakim Akhunov; Dwaipayan Biswas; Emil Karimov; Arvind Sharma; Hyungrock Oh; Maarten Rosmeulen; Julien Ryckaert; James Myers (ISCAS, 2025)

3D SRAM Disaggregation in Advanced CMOS Nodes using Hybrid Bonding Technology. - Bhawana Kumari; Anurag Swarnkar; Dawit Burusie Abdi; Fernando García-Redondo; James Myers; Julien Ryckaert; Jaydeep Kulkarni; Dwaipayan Biswas (ISCAS, 2025)

3D IGZO Charge-Coupled Memory DTCO & STCO Analysis for Compute-near-Memory Applications. - Bowen Wang; Khakim Akhunov; Hyungrock Oh; Fernando García-Redondo; Yukai Chen; Arvind Sharma; Jiacong Sun; Sahan Gamage; Maarten Rosmeulen; Swaraj Bandhu Mahato; Rishabh Kishore; Subhali Subhechha; et al. (ISCAS, 2025)

Live Demonstration: N2 Nanosheet Pathfinding-PDK. - Chaohan Wang; Jack Cousins; Anita Farokhnejad; Marie Garcia Bardon; Julien Ryckaert (ISCAS, 2025)

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. - Sudipta Das; Samuel Riedel; Mohamed Naeim; Moritz Brunion; Marco Bertuletti; Luca Benini; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology. - Yukai Chen; Massimiliano Di Todaro; Bjorn Vermeersch; Herman Oprins; Daniele Jahier Pagliari; Julien Ryckaert; Dwaipayan Biswas; James Myers (CoRR, 2025)

Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes. - Lorenzo Ruotolo; Lara Orlandic; Pengbo Yu; Moritz Brunion; Daniele Jahier Pagliari; Dwaipayan Biswas; Giovanni Ansaloni; David Atienza; Julien Ryckaert; Francky Catthoor; Yukai Chen (CoRR, 2025)