Redundant CORDIC Rotator Based on Parallel Prediction. - Elisardo Antelo; Javier D. Bruguera; Julio Villalba; Emilio L. Zapata (IEEE Symposium on Computer Arithmetic, 1995)

Digit On-line Large Radix CORDIC Rotator. - Roberto R. Osorio; Elisardo Antelo; Javier D. Bruguera; Julio Villalba; Emilio L. Zapata (ASAP, 1995)

CORDIC Architectures with Parallel Compensation of the Scale Factor. - Julio Villalba; José Antonio Hidalgo López; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (ASAP, 1995)

A fast Hough transform for segment detection. - Nicolás Guil; Julio Villalba; Emilio L. Zapata (IEEE Trans. Image Process., 1995)

Radix-4 Vectoring Cordic Algorithm And Architectures. - Julio Villalba; J. C. Arrabal; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (ASAP, 1996)

High Radix Cordic Rotation Based on Selection by Rounding. - Elisardo Antelo; Javier D. Bruguera; Tomás Lang; Julio Villalba; Emilio L. Zapata (Euro-Par, Vol. II, 1996)

Cordic based parallel/pipelined architecture for the Hough transform. - Javier D. Bruguera; Nicolás Guil; Tomás Lang; Julio Villalba; Emilio L. Zapata (J. VLSI Signal Process., 1996)

Low latency word serial CORDIC. - Julio Villalba; Tomás Lang (ASAP, 1997)

High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. - Elisardo Antelo; Julio Villalba; Javier D. Bruguera; Emilio L. Zapata (IEEE Trans. Computers, 1997)

A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (SCAN, 1998)

Parallel Compensation of Scale Factor for the CORDIC Algorithm. - Julio Villalba; Tomás Lang; Emilio L. Zapata (J. VLSI Signal Process., 1998)

Radix-4 Vectoring CORDIC Algorithm and Architectures. - Julio Villalba; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (J. VLSI Signal Process., 1998)

Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (IEEE Symposium on Computer Arithmetic, 1999)

Arithmetic Unit for the Computation of Interval Elementary Functions. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (EUROMICRO, 1999)

A Hardware Algorithm for Variable-Precision Logarithm. - Javier Hormigo; Julio Villalba; Michael J. Schulte (ASAP, 2000)

MMX-Like Architecture Extension to Support the Rotation Operation. - Julio Villalba; Javier Hormigo; Mario A. González; Emilio L. Zapata (IEEE International Conference on Multimedia and Expo (III), 2000)

Polynomial Evaluation on Multimedia Processors. - Julio Villalba; Gerardo Bandera; Mario A. González; Javier Hormigo; Emilio L. Zapata (ASAP, 2002)

Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. - Joaquín Olivares 001; Javier Hormigo; Julio Villalba; Ignacio Benavides (FPL, 2004)

Evaluation of Elementary Functions Using Multimedia Features. - Gerardo Bandera; Mario A. González; Julio Villalba; Javier Hormigo; Emilio L. Zapata (IPDPS, 2004)

CORDIC Processor for Variable-Precision Interval Arithmetic. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (J. VLSI Signal Process., 2004)

Low Latency Pipelined Circular CORDIC. - Elisardo Antelo; Julio Villalba (IEEE Symposium on Computer Arithmetic, 2005)

On-line Multioperand Addition Based on On-line Full Adders. - Julio Villalba; Javier Hormigo; Jose M. Prades; Emilio L. Zapata (ASAP, 2005)

Pipelined Range Reduction for Floating Point Numbers. - Francisco J. Jaime; Julio Villalba; Javier Hormigo; Emilio L. Zapata (ASAP, 2006)

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. - Joaquín Olivares 001; Ignacio Benavides; Javier Hormigo; Julio Villalba; Emilio L. Zapata (FPL, 2006)

SAD computation based on online arithmetic for motion estimation. - Joaquín Olivares 001; Javier Hormigo; Julio Villalba; Ignacio Benavides; Emilio L. Zapata (Microprocess. Microsystems, 2006)

Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations. - Julio Villalba; Tomás Lang; Mario A. González (IEEE Trans. Computers, 2006)

Improving the Throughput of On-line Addition for Data Streams. - Julio Villalba; Javier Hormigo; Tomás Lang (ASAP, 2007)

SIMD Enhancements for a Hough Transform Implementation. - Francisco J. Jaime; Javier Hormigo; Julio Villalba; Emilio L. Zapata (DSD, 2008)

New SIMD instructions set for image processing applications enhancement. - Francisco J. Jaime; Javier Hormigo; Julio Villalba; Emilio L. Zapata (ICIP, 2008)

A Low-Latency Pipelined 2D and 3D CORDIC Processors. - Elisardo Antelo; Julio Villalba; Emilio L. Zapata (IEEE Trans. Computers, 2008)

Pipelined Architecture for Additive Range Reduction. - Francisco J. Jaime; Julio Villalba; Javier Hormigo; Emilio L. Zapata (J. Signal Process. Syst., 2008)

Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. - Álvaro Vázquez; Julio Villalba; Elisardo Antelo (IEEE Symposium on Computer Arithmetic, 2009)

Efficient Implementation of Carry-Save Adders in FPGAs. - Javier Hormigo; Manuel Ortiz; Francisco J. Quiles 002; Francisco J. Jaime; Julio Villalba; Emilio L. Zapata (ASAP, 2009)

Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator. - Carlos Diego Moreno-Moreno; Francisco J. Quiles 002; Manuel Ortiz; María Brox; Javier Hormigo; Julio Villalba; Emilio L. Zapata (ICECS, 2009)

UCORE: Reconfigurable Platform for Educational Purposes. - Francisco J. Quiles 002; Manuel Ortiz; María Brox; Carlos Diego Moreno-Moreno; Javier Hormigo; Julio Villalba (ReConFig, 2010)

Enhanced Scaling-Free CORDIC. - Francisco J. Jaime; Miguel A. Sanchez; Javier Hormigo; Julio Villalba; Emilio L. Zapata (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

High-Speed Algorithms and Architectures for Range Reduction Computation. - Francisco J. Jaime; M. A. Sánchez; Javier Hormigo; Julio Villalba; Emilio L. Zapata (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Decimal online multioperand addition. - Carlos Garcia-Vega; Sonia González-Navarro; Julio Villalba; Emilio L. Zapata (ACSCC, 2012)

On-line Decimal Adder with RBCD Representation. - Carlos Garcia-Vega; Sonia González-Navarro; Julio Villalba-Moreno; Emilio L. Zapata (ASAP, 2012)

Redundant Floating-Point Decimal CORDIC Algorithm. - Álvaro Vázquez; Julio Villalba-Moreno; Elisardo Antelo; Emilio L. Zapata (IEEE Trans. Computers, 2012)

Radix-2 Multioperand and Multiformat Streaming Online Addition. - Julio Villalba; Tomás Lang; Javier Hormigo (IEEE Trans. Computers, 2012)

Efficient floating-point representation for balanced codes for FPGA devices. - Julio Villalba; Javier Hormigo; Francisco Corbera; Mario A. González; Emilio L. Zapata (ICCD, 2013)

Multioperand Redundant Adders on FPGAs. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (IEEE Trans. Computers, 2013)

Optimizing DSP circuits by a new family of arithmetic operators. - Javier Hormigo; Julio Villalba (ACSSC, 2014)

Simplified floating-point units for high dynamic range image and video systems. - Javier Hormigo; Julio Villalba (ISCE, 2015)

Digit Recurrence Floating-Point Division under HUB Format. - Julio Villalba-Moreno (ARITH, 2016)

Decimal Multiformat Online Addition. - Carlos Garcia-Vega; Sonia González-Navarro; Pedro Balboa-La Chica; Julio Villalba-Moreno (IEEE Trans. Computers, 2016)

New Formats for Computing with Real-Numbers under Round-to-Nearest. - Javier Hormigo; Julio Villalba (IEEE Trans. Computers, 2016)

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. - Javier Hormigo; Julio Villalba (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Floating Point Square Root under HUB Format. - Julio Villalba-Moreno; Javier Hormigo (ICCD, 2017)

Introduction to the Special Issue on Computer Arithmetic. - Javier Hormigo; Jean-Michel Muller; Stuart F. Oberman; Nathalie Revol; Arnaud Tisserand; Julio Villalba-Moreno (IEEE Trans. Computers, 2017)

HUB Floating Point for Improving FPGA Implementations of DSP Applications. - Javier Hormigo; Julio Villalba (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Unbiased Rounding for HUB Floating-Point Addition. - Julio Villalba-Moreno; Javier Hormigo; Sonia González-Navarro (IEEE Trans. Computers, 2018)

Reproducible Summation Under HUB Format. - Julio Villalba-Moreno; Javier Hormigo; Francisco J. Jaime (ARITH, 2019)

Fast HUB Floating-Point Adder for FPGA. - Julio Villalba; Javier Hormigo; Sonia González-Navarro (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Floating-Point Fused Multiply-Add under HUB Format. - Javier Hormigo; Julio Villalba-Moreno; Sonia Gonzalez-Navarro (ARITH, 2020)

High-Radix Formats for Enhancing Floating-Point FPGA Implementations. - Julio Villalba; Javier Hormigo (Circuits Syst. Signal Process., 2022)

Floating Point HUB Adder for RISC-V Sargantana Processor. - Gerardo Bandera; Javier Salamero; Miquel Moretó; Julio Villalba (CoRR, 2024)

Teaching Experiences using the RVfpga Package. - Daniel Chaver; Sarah L. Harris; Luis Piñuel; Olof Kindgren; R. Kravitz; José Ignacio Gómez; Fernando Castro; Katzalin Olcoz; Julio Villalba; A. Grinshpun; F. Gabbay; L. Seed; et al. (CoRR, 2024)