A thread partitioning algorithm in low power high-level synthesis. - Jumpei Uchida; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

A processor core synthesis system in IP-based SoC design. - Naoki Tomono; Shunitsu Kohara; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2005)

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. - Nozomu Togawa; Hideki Kawazu; Jumpei Uchida; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS (4), 2005)

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. - Hideki Kawazu; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. - Shunitsu Kohara; Naoki Tomono; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2006)

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. - Jumpei Uchida; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Electron., 2006)